Pub. Date:
Springer Netherlands
Functional Design Errors in Digital Circuits: Diagnosis Correction and Repair / Edition 1

Functional Design Errors in Digital Circuits: Diagnosis Correction and Repair / Edition 1


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Product Details

ISBN-13: 9789048181124
Publisher: Springer Netherlands
Publication date: 11/05/2010
Series: Lecture Notes in Electrical Engineering , #32
Edition description: Softcover reprint of hardcover 1st ed. 2009
Pages: 200
Product dimensions: 6.10(w) x 9.25(h) x 0.02(d)

About the Author

Winner of the EDAA (European Design Automation Association) Outstanding Monograph Award in the Verification section. Co-authors Bertacco and Markov are existing Springer authors

Table of Contents

Dedication. List of Figures. List of Tables. Preface. Part I Background and Prior Art. 1. INTRODUCTION. 1.1 Design Trends and Challenges. 1.2 State of the Art. 1.3 Our Approach. 1.4 Key Innovations and Book Outline. 2. CURRENT LANDSCAPE IN DESIGN AND VERIFICATION. 2.1 Front-End Design. 2.2 Back-End Logic Design. 2.3 Back-End Physical Design. 2.4 Post-Silicon Debugging. 3. FINDING BUGS AND REPAIRING CIRCUITS. 3.1 Simulation-Based Verification. 3.2 Formal Verification. 3.3 Design for Debugging and Post-Silicon Metal Fix. Part II FogClearMethodologies and Theoretical Advances in Error Repair. 4. CIRCUIT DESIGN AND VERIFICATION METHODOLOGIES. 4.1 Front-End Design. 4.2 Back-End Logic Design. 4.3 Back-End Physical Design. 4.4 Post-Silicon Debugging. 5. COUNTEREXAMPLE-GUIDED ERROR-REPAIR FRAMEWORK. 5.1 Background. 5.2 Error-Correction Framework for Combinational Circuits. 6. SIGNATURE-BASED RESYNTHESIS TECHNIQUES. 6.1 Pairs of Bits to be Distinguished (PBDs). 6.2 Resynthesis Using Distinguishing-Power Search. 6.3 Resynthesis Using Goal-Directed Search. 7. SYMMETRY-BASED REWIRING. 7.1 Background. 7.2 Exhaustive Search for Functional Symmetries. 7.3 Post-Placement Rewiring. 7.4 Experimental Results. 7.5 Summary. Part III FogClear Components. 8. BUG TRACE MINIMIZATION. 8.1 Background and PreviousWork. 8.2 Analysis of Bug Traces. 8.3 Proposed Techniques. 8.4 Implementation Insights. 8.5 Experimental Results. 8.6 Summary. 9. FUNCTIONAL ERROR DIAGNOSIS AND CORRECTION. 9.1 Gate-Level Error Repair for Sequential Circuits. 9.2 Register-Transfer-Level Error Repair. 9.3 Experimental Results. 9.4 Summary. 10. INCREMENTAL VERIFICATION FOR PHYSICAL SYNTHESIS. 10.1 Background. 10.2 Incremental Verification. 10.3 Experimental Results. 10.4 Summary. 11. POST-SILICON DEBUGGING AND LAYOUT REPAIR. 11.1 Physical Safeness and Logical Soundness. 11.2 New ResynthesisTechnique—SafeResynth. 11.3 Physically-Aware Functional Error Repair. 11.4 Automating Electrical Error Repair. 11.5 Experimental Results. 11.6 Summary. 12. METHODOLOGIES FOR SPARE-CELL INSERTION. 12.1 Existing Spare-Cell Insertion Methods. 12.2 Cell Type Analysis. 12.3 Placement Analysis. 12.4 Our Methodology. 12.5 Experimental Results. 12.6 Summary. 13. CONCLUSIONS. Index. References.

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