HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs Using VHDL or Verilog available in Hardcover
This book is the Electronic Engineers' comprehensive VHDL/Verilog modeling guide for ASIC and FPGAs
This book describes, and shows by practical example, how to design ASIC and FPGA devices using the two industry standard hardware description languages, VHDL and Verilog. The emphasis is on RTL modeling using synthesis within a top-down design methodology.
With this book learn how to:
- make chip design easier,
- improve your design productivity,
- design efficient synthesizable models,
- write good HDL test harnesses,
- acquire good design and modeling practices.
Electronic Engineers and students will find this complete VHDL/Verilog modeling guide to be an essential addition to their technical resources.
|Product dimensions:||8.00(w) x 11.00(h) x (d)|
About the Author
Douglas Smith was born in England, and began his career with a four year apprenticeship in a company developing and manufacturing radiation monitoring equipment. He received a B.Sc. in Electrical and Electronic Engineering from Bath University, England, in 1981. He worked at a number of companies in England performing digital design and project management of microprocessor based circuit boards and associated ICs. These IC's included PLD, FPGA, gate array ASICs and standard cell ASIC devices for applications such as ring laser gyro control and frequency hopping radios. He then moved into the EDA industry by becoming applications manager and then product marketing manager for all synthesis products at GenRad Ltd. When GenRad exited from the EDA industry he moved to the USA to Intergraph Electronics, now VeriBest Incorporated, where he is now a member of the technical staff.
Table of Contents
Chapter One: Introduction
- Introduction ..... 3
ASIC and FPGA devices ..... 3
Top-Down Design Methodology ..... 5
Hardware Description Languages (HDLs) ..... 8
Design Automation Tools ..... 14
HDL support for synthesis ..... 25
- Introduction ..... 29
Combinational logic optimization ..... 30
A typical design constraint scenario ..... 32
- Design Entities ..... 39
VHDL Design Entity ..... 39
Verilog Design Entity ..... 40
Code Structure ..... 41
Declaration statements ..... 41
Concurrent statements ..... 41
Sequential statements ..... 41
Data Types and Data Objects ..... 44
VHDL Data Types ..... 45
VHDL Data Objects ..... 46
Verilog Data Types ..... 47
Verilog Data Objects ..... 47
Expressions ..... 48
Operands ..... 48
Literal Operands ..... 49
Identifier Operands ..... 50
Aggregate Operands (VHDL) ..... 51
Function Call Operands ..... 52
Index & Slice Name Operands ..... 53
Qualified Expression Operands (VHDL) ..... 54
Type Conversion Operands (VHDL) ..... 56
Record & Record Element Operands (VHDL) ..... 57
Operators ..... 59
Overloaded Operators (VHDL) ..... 59
Arithmetic Operators ..... 63
Sign Operators ..... 64
Relational Operators ..... 64
Equality & Inequality Operators ..... 65
Logical Comparison Operators ..... 66
Logical Bit-wise Operators ..... 68
Shift Operators ..... 69
Concatenation & Verilog replication Operators ..... 70
ReductionOperators (Verilog) ..... 70
Conditional Operator (Verilog) ..... 71
- Introduction ..... 75
Design and Modeling Recommendations ..... 75
- 1. Design and process recommendations ..... 75
2. Power reduction recommendations ..... 75
3. Design for test (OFT) and test issues ..... 75
4. Test harnesses recommendations ..... 76
5. General HDL modeling recommendations ..... 76
6. Ensuring simulation accuracy ..... 77
7. Improving simulation speed ..... 77
8. Synthesis modeling recommendations ..... 78
9. Joint simulation and synthesis modeling recommendations ..... 79
- 1. Output and buffer port modes (VHDL) ..... 79
2. Width qualification of unconstrained arrays (VHDL) ..... 80
3.Operators to the left of the assignment operator ..... 80
4. Unconstrained subprogram parameters in reusable models (VHDL) ..... 81
5. Invisible subprograms from separate packages (VHDL) ..... 82
6. Subprogram overloading using type integer and subtype natural (VHDL) ..... 82
7. Concatenation in the expression of a subprogram's formal list (VHDL) ..... 82
- 1. Full sensitivity/event list (VHDL & Verilog) ..... 83
2. Reversing a vectored array direction (VHDL & Verilog) ..... 83
3. True leading edge detection - wait and if (VHDLJ ..... 84
4. Order dependency of concurrent statements ..... 84
- 1. Non-static data objects and non-static loops (VHDL & Verilog) ..... 85
- 1. When to use others (VHDL) and default (Verilog) ..... 87
2. Signal and variable assignments (VHDL) ..... 89
3. Blocking and non-blocking procedural assignments (Verilog) ..... 94
4. Don't care inputs to a case statement (VHDL & Verilog) ..... 96
5. Don't care outputs from a case statement (VHDL & Verilog) ..... 97
6. Comparing vector array types of different width (VHDL) ..... 98
- 1. Using Attributes (VHDL) ..... 99
2. Using Packages (VHDL) ..... 103
3. Operator and subprogram overloading (VHDL) ..... 105
- 1. Design and process recommendations ..... 75
VHDL and Verilog are covered equally throughout this book. Code examples she on the left and Verilog on the right because VHDL became a standard first. All language
reserved words are shown emboldened. Also, all HDL code related issues in the text apply equally to VHDL and Verilog unless explicitly stated otherwise. Where synthesized circuits are shown they are a result of synthesizing either the VHDL or Verilog version of the associated model.
This book is divided into 12 chapters, a glossary and two appendices.
Chapter 1, "Introduction", defines what ASIC and FPGA devices are, and the crireria for choosing which to use in a given application. Hardware description languages are defined and a comprehensive listing of comparative features between VHDL and Verilog is given. Electronic Design Automation (EDA) tools are discussed with a particular emphasis on synthesis tools.
Chapter 2, "Synthesis Constraint and Optimization Tutorials", shows the effect of different constraints on the synthesized circuit of a particular design. Also, -a typical design constraint scenario is posed and a description of how constraints for it are specified, described. For completeness, command line optimization commands are included for the VeriBest Synthesis tools.
Chapter 3, "Language Fundamentals", introduces the fundamentals of the VHDL and Verilog hardware description languages. Code structure is described by first definining the principle of design units and how they link together. The code structure of subsetions within a design unit are described all the way down to subfunctions. Assignments are also defined together with theexpressions within them. Includes a fully detailed description of the operands and operators that make up an expression.
Chapter 4, "Design/Modeling Recommendations, Issues and Techniques", is one of the most important chapters to the practicing digital design engineer. It provides a list of recommendations, issues and techniques to consider when designing ASICs or FPGAs, from both a design and HDL modeling perspective.
Chapter 5, "Structuring a Design", is devoted to structuring HDL code and hence inferred hardware structure when modeling at the register transfer level. Code constructs are grouped and discussed separately based on their level of granularity.
Chapter 6, "Modeling Combinational Logic Circuits", shows HDL models of commonly used circuit functions that are implemented using combinational logic only. In most cases different ways of modeling the same circuit is shown. Circuit functions covered include: multiplexers, encoders, priority encoders, decoders, comparators and ALUs.
Chapter 7, "Modeling Synchronous Logic Circuits", shows how D-type latches and D-type flip- flops are inferred in HDL models. Also included, are various models of linear-feedback shift- registers and counters.
Chapter 8, "Modeling Finite State Machines", covers in detail the different aspects of modeling finite state machines. Shown are: good and bad coding styles, when resets are needed for fail safe behavior, state machines with Mealy or Moore type outputs, state machines with additional synchronous logic modeled in the code of the state machine, and multiple interactive state machines.
Chapter 9, "Circuit Functions Modeled Combinational or Synchronously", describes how shifters, adders, subtracters, multipliers and dividers may be modeled for a combinational or synchronous logic implementation.
Chapter 10, "Tri-State Buffers", contains various examples of how tri-state buffers are inferred.
Chapter 11, "Writing Test Harnesses", describes the structure of a simulation test harness and all related issues. Detailed examples show how input stimuli may be generated, and how outputs from the model under test may be automatically monitored and tested against reference data.
Chapter 12, "Practical Modeling Examples", contains five larger modeling examples. Each example is posed as a problem and solution. The first shows how an internal tristate bus is used to reduce circuit area. The second example is of a digital alarm clock. The third example is a three-way round- robin priority encoder used to arbitrate between three microprocessors accessing the same RAM. The fourth example is of a circuit that computes the greatest common divisor of two inputs. It is modeled at the algorithmic level in C, VHDL and Verilog, and again at the RTL level in VHDL and Verilog, and uses common test data files. Test harnesses for the RTL level models are also shown. The fifth example is a model of an error detection and correction circuit that sits between a microprocessor and RAM. Critical data is stored in the RAM along with parity check bits. When data is retrieved single bit errors are detected and corrected, while double bit errors are simply detected and an interrupt generated.
Glossary, contains the definition of over 200 terms.
Appendix A, "VHDL", contains reference information relating to VHDL: reserved words, predefined attributes, listings of packages STANDARD, TEXTIO, STD_LOGIC_1164 and NUMERIC_STD, and reference information relating to VHDL constructs and where they are used.
Appendix B, "Verilog", contains reference information relating to Verilog: reserved words, compiler directives, system tasks and functions, and reference information relating to VHDL constructs and where they are used.
Every effort has been made to make this book as complete and as accurate as possible. However, there may be mistakes both typographical and in content. Therefore, this text should be used only as a general guide and not the ultimate reference source on the two languages. Please refer to the respective LRMs for syntax accuracy.
The author and publisher shall not be liable for any direct or indirect damages arising from any use, direct or indirect, of the examples provided in this book.
Most Helpful Customer Reviews
A dual reference book for VHDL and Verilog. For someone skilled in one language it quickly allows you to understand the syntax and capabilities of the other language. Section on VHDL variables versus signals is very good an provides good understanding of the different coding styles.