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Cengage Learning
HDL Programming Fundamentals: VHDL and Verilog / Edition 1

HDL Programming Fundamentals: VHDL and Verilog / Edition 1

by Nazeih M Botros


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Product Details

ISBN-13: 9781584508557
Publisher: Cengage Learning
Publication date: 11/18/2005
Series: Charles River Media Computer Engineering Series
Edition description: Book & CD
Pages: 528
Product dimensions: 7.70(w) x 9.70(h) x 1.55(d)
Age Range: 3 Months

About the Author

Nazeih M. Botros (Carbondale, IL) is a professor in the Department of Electrical and Computer Engineering at the University of Southern Illinois. He has a Ph.D. in electrical engineering from the University of Oklahoma, and over 25 years of teaching experience in areas including Instrumentation, Artificial Intelligence, Computer Architecture, Digital Hardware Design, HDL, and Digital Signal Analysis. He has published articles in Journal of Control & Intelligent Systems, International Journal of Robotics and Automation, International Journal of Modeling and Simulation, and International Journal of Microcomputer Applications, and has spoken at various industry conferences.

Table of Contents

Preface Chapter 1 Introduction 1.1 Why HDL? 1.2 A Brief History of HDL 1.3 Structure of the HDL Module 1.4 Operators 1.5 Data Types 1.6 Styles (Types) of Descriptions 1.7 Simulation and Synthesis 1.8 Brief Comparison of VHDL and Verilog 1.9 Summary 1.10 Exercises 1.11 References Chapter 2 Data-Flow Descriptions 2.1 Highlights of Data-Flow Description 2.2 Structure of the Data-Flow Description 2.3 Data Type—Vectors 2.4 Common Programming Errors 2.5 Summary 2.6 Exercises 2.7 References Chapter 3 Behavioral Descriptions 3.1 Behavioral Description Highlights 3.2 Structure of the HDL Behavioral Description 3.3 The VHDL Variable-Assignment Statement 3.4 Sequential Statements 3.5 Common Programming Errors 3.6 Summary 3.7 Exercises 3.8 References Chapter 4 Structural Descriptions 4.1 Highlights of Structural Descriptions 4.2 Organization of the Structural Description 4.3 Binding 4.4 State Machines 4.5 Generate (HDL), Generic (VHDL), and Parameter (Verilog) 4.6 Summary 4.7 Exercises 4.8 References Chapter 5 Switch-Level Descriptions 5.1 Highlights of the Switch-Level Description 5.2 Useful Definitions 5.3 Single NMOS and PMOS Switches 5.4 Switch-Level Description of Primitive Gates 5.5 Switch-Level Description of Simple Combinational Logics 5.6 Switch-Level Description of Simple Sequential Circuits 5.7 Bidirectional Switches 5.8 Summary 5.9 Exercises 5.10 References Chapter 6 Procedures, Tasks, and Functions 6.1 Highlights of Procedures, Tasks, and Functions 6.2 Procedures and Tasks 6.3 Functions 6.4 Summary 6.5 Exercises 6.6 References Chapter 7 Mixed-Type Descriptions 7.1 Why Mixed-Type Description? 7.2 VHDL User-Defined Types 7.3 VHDL Packages 7.4 Mixed-Type Description Examples 7.5 Summary 7.6 Exercises 7.7 References Chapter 8 Advanced HDL Descriptions 8.1 File Processing 8.2 Examples of File Processing 8.3 VHDL Record Type 8.4 Summary 8.5 Exercises 8.6 References Chapter 9 Mixed-Language Descriptions 9.1 Highlights of Mixed-Language Description 9.2 How to Invoke One Language from the Other 9.3 Mixed-Language Description Examples 9.4 Limitations of Mixed-Language Description 9.5 Summary 9.6 Exercises 9.7 References Chapter 10 Synthesis Basics 10.1 Highlights of Synthesis 10.2 Synthesis Information from Entity and Module 10.3 Mapping Process and Always in the Hardware Domain 10.4 Summary 10.5 Exercises 10.6 References Appendix A Creating a Project in Xilinx 7.1 Using VHDL or Verilog Appendix B Summary of HDL Commands Appendix C About the CD-ROM Index

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