ISTFA 2003: Proceedings of the 29th International Symposium for Testing and Failure Analysis, 2-6 November 2003, Santa Clara, CA

ISTFA 2003: Proceedings of the 29th International Symposium for Testing and Failure Analysis, 2-6 November 2003, Santa Clara, CA

by A S M International

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Product Details

ISBN-13: 9780871707888
Publisher: A S M International
Publication date: 01/01/2003
Pages: 700

Table of Contents

Session 1Advanced Techniques
Scanning Magnetoresistive Microscopy for Die-Level Sub-Micron Current Density Mapping2
High Resolution Current Imaging by Direct Magnetic Field Sensing6
Fault Isolation of High Resistance Defects Using Comparative Magnetic Field Imaging9
High Resolution Backside Thermography Using a Numerical Aperture Increasing Lens14
Session 2Optical Techniques
Study of Critical Factors Determining Latchup Sensitivity of ICs Using Emission Microscopy19
New Applications of Thermal Laser Signal Injection Microscopy (T-LSIM)25
PC Card Based Optical Probing of Advanced Graphics Processor Using Time Resolved Emission36
Time-Resolved Optical Measurements from 0.13 [mu]m CMOS Technology Microprocessor Using a Superconducting Single-Photon Detector40
IC Diagnostic with Time Resolved Photon Emission and CAD Auto-Channeling45
Session 3Package Level Analysis 1
3D X-ray Computed Tomography (CT) for Electronic Packages56
High-Angle Electron Microscopy Technique for Analysis of Thin Film Contamination on IC Package Exteriors62
Solder Bump Defects in Ceramic Flip Chip Packages and Their Acoustic Signatures68
Copper Bond Over Active Circuit (BOAC) and Copper Over Anything (COA) Failure Analysis76
Investigation of Bond-Pad Related Inter-Metal Dielectric Crack82
Session 4Sample Preparation 1
Enhanced SEM Doping Contrast87
Interconnect and Gate Level Delayering Techniques for Cu/Low k Technology Failure Analysis90
Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis99
A Novel Approach to Front-Side Deprocessing for Thinned Die after Backside Failure Isolation105
Session 5System Level Analysis
Dynamic Infrared System Level Fault Isolation111
X-ray Laminography Benchmarking and Failure Analysis of Solder Joint Interfaces120
XRF Correlation of Board Reseats Due to Intermittent Failures from the Use of Thin Gold Plating finish on the Contact Fingers125
Session 6Metrology and Materials Analysis 1
Real Time SEM Imaging of FIB Milling Processes for Extended Accuracy on TEM Samples for EFTEM Analysis132
A Method for Exact Determination of DRAM Deep Trench Surface Area140
A Review of TEM Observations of Failures of the Memory Cell in a Deep Trench Capacitor DRAM144
The Effect of TEM Specimen Preparation Method on Ultra-Thin Gate Dielectric Analysis153
Forward Scattered Scanning Electron Microscopy for Semiconductor Metrology and Failure Analysis158
Session 7Failure Analysis Process
Contributions of a Formal Analysis Metaprocess to Breakthrough Failure Analysis Results167
SRAM Failure Analysis Strategy177
VLSI Design for Functional Failure Analysis in the [less than sign] 90 nm and Flip-Chip Era184
Identification of an I[subscript DDQ] Failure Mechanism Using a Variety of Front and Backside Analytical Techniques191
Novel Application of Transmission Electron Microscopy and Scanning Capacitance Microscopy for Defect Root Cause Identification and Yield Enhancement197
Session 8Metrology and Materials Analysis 2
Contact Failure Due to Particulate Defect in a 0.13 [mu]m CMOS Process206
Microhardness Testing on Via Fill Material for Via In Pad Technology209
Application of ToF-SIMS to Airborne Organic Contamination Analysis215
Session 9Test 1
Yield-Modeling and Test Oriented Taxonomy of IC Structure Deformations222
Analysis of IC Manufacturing Process Deformations: An Automated Approach Using SRAM Bit Fail Maps232
Electrical Failure Analysis and Characterization of Leakage Paths Leading to Single Cell Failures in 128Mbit SDRAMs242
Session 10Posters - Case Studies
A Study on Fluorine-Induced Corrosion on Microchip Aluminum Bondpads249
Advanced Process Defect Detection by Using Dynamic Bias Condition and MCT Camera256
Via Chain Failure Analysis Using a Combination of E-Beam and Optical Beam Techniques259
Session 10Posters - ESD Failure
ESD Failure Signature Differences in the Devices Core Logic and Protection Structures - A Case Study262
ESD: Correlation between Electrical Signature and Failure Modes272
Session 10Posters - Sample Prep
Semi-Automated Cross-Section Preparation Process for Complex Multi-Face Perimeter Samples278
FIB Micro-Pillar Sampling of Si Devices and its 3D Observation282
Recent Developments in Automated Sample Preparation for FESEM288
Wet Delineation of SEM Samples Having Cu Interconnects297
An Evolution in Plastic Decapsulation Process Improvement301
Session 10Posters - Techniques
Obtaining Low Contact Resistance for Physical Sub-Micron Fault Isolation305
Near IR Continuous Wavelength Spectroscopy of Photon Emissions from Semiconductor Devices311
Defect Isolation and Characterization in Contacts by Using Primary Voltage Adjustment317
A Flexible, Low Cost Test System for Failure Analysis of High Power Mixed Signal ASICs320
Photoemission and OBIRCH Analysis with Solid Immersion Lens (SIL)325
Session 11Circuit Edit for FA, FI and Debug
Voltage Contrast like Imaging of N-Wells331
Improvements of Secondary Electron Imaging and Endpoint Detection in Focused Ion Beam Circuit Modification338
Modeling Secondary Electron Emission from High Aspect Ratio Holes343
The Impact of Feature Packing Density on FIB Editing of Advanced Technology Ics348
Small Via High Aspect Ratio Circuit Edit: Challenges, Techniques and Developments355
Session 12Die Level Fault Isolation
Improved SRAM 6T Bit Cell Failure Analysis Using MCSpice Bit Cell Defect Modeling363
Laser Stimulation Applied to Dynamic IC Diagnostics371
Speed Path Analysis: A Connection Between Speed Degradation, Silicon Dislocations, and Light Induced Voltage Alteration378
Fault Localization of a Scan Shift Problem on Integrated Logic Designs384
Application of Scan Based FA and Advanced Passive Voltage Contrast Technique in Defect Isolation391
Session 13SPM Techniques
Quantitative Interpretation of Scanning Capacitance Microscope Images as Two-Dimensional Dopant Profiles398
Advanced Analysis of Thin and Ultrathin SiO[subscript 2] Films and SiO[subscript 2]/Si Interfaces with Combined Atomic Force Microscopy Methods406
Fault Localization in Contact Level by Using Conductive Atomic Force Microscopy413
Characterization of Interconnect Defects Due to Electromigration Using Scanning Thermal Microscopy419
Session 14Optoelectronic Devices
Failure Analysis of Vertical Cavity Surface Emission Laser Diodes426
Indium Tin Oxide (ITO) Film Removal Technique for Failure Analysis on Packaged Optoelectronic Devices431
Session 15Discretes, Passive
MIM Capacitor Reliability Fault Identification Using IR Microthermography and Automated Deprocessing: A Case Study437
Magnetic Emission Mapping for Passive Integrated Components Characterisation440
Session 16Sample Preparation 2
Backside Imaging and AFM Profiling of Tunnel Oxide, Poly 1, ONO and Poly 2 Layers on Flash Devices447
Sample Preparation Techniques for Analysis and Debug of Circuits with Cu Inductors and Thick Organic Dielectric452
Laser Interferometer Specimen Preparation of PCB Assembled Components at Second Level Interconnect for In-plane Shear Strain Measurements456
A Novel Fault Isolation Technique for Identifying Deep Sub-Micron Defects465
Session 17Yield Enhancement
Failure Analysis Case Study in 0.18[mu]m Flash Memory Devices and Root Cause Identification471
Characterization of Sub 130 Nanometer Gate Length SOI MOSFET Devices Exhibiting Short Channel Effects478
Session 18Test 2
Mechanical and Electrical Characterization of an IC Bond Pad Stack Using a Novel In-Situ Methodology486
A Multi-Stage Approach to Fault Identification Using Fault Tuples496
Power Supply Noise Analysis Using Neural Network and Genetic Algorithm Based on Automatic Test Equipment506
Author Index515

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