Pub. Date:
Springer US
Mixed Design of Integrated Circuits and Systems / Edition 1

Mixed Design of Integrated Circuits and Systems / Edition 1


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Product Details

ISBN-13: 9780792381167
Publisher: Springer US
Publication date: 01/31/1998
Series: The Springer International Series in Engineering and Computer Science , #434
Edition description: Softcover reprint of the original 1st ed. 1998
Pages: 237
Product dimensions: 6.10(w) x 9.25(h) x 0.02(d)

Table of Contents

I: Analog Circuits Design. 1. Multichannel Low Noise, Low Power Analogue Readout Chip for Silicon Strip Detectors; W. Bialas, et al. 2. Design Methodology for Current Conveyor Based Continuous-Time Field-Programmable Analog Array; R. Grisel, et al. 3. RF Amp IC for Optical Disc Player; Chun-Sup Kim, et al. 4. CMOS Current Conveyor Design and Macromodel; S. Kuta, et al. 5. Behavioural Noise Modelling of Cross-Coupled Ring Oscillators; L.J. Opalski. 6. A 27 MHz Fully-Balanced OTA-C Filter in 2muM CMOS Technology; B. Pankiewicz, et al. 7. Programming Analog Non- Volatile Memories; E. Tournier, J.-L. Noullet. 8. Four-Quadrant CMOS Amplifier for Low-voltage Current-mode Analog Signal Processing; R. Wojtyna, et al. II: Power Devices and Thermal Aspects. 9. Application of Inverse Problems to IC Temperature Estimation; M. Janicki, et al. 10. Thermal Model for MCM's; F. Masana. 11. Contribution of Radiation in Heat Dissipation in Electronic Devices; B. Wiecek, G. De Mey. 12. Modelling and Synthesis of Electro-Thermal Microdevices; W. Wójciak, et al. III: Microsystems and Neural Networks. 13. Layout Optimization of CMOS Phototransistors; M. Moreno, et al. 14. Multilayer Piezoelectric Sensors on the Basis of the PZT Type Ceramics; D. Czekaj, et al. 15. Artificial Neural Network Mixed-Signal Prototype System for Model Parameter Identification; A. Materka, et al. 16. Mixed A/D VLSI Architecture for the Emulation of Neuro-Fuzzy Models; J.M. Moreno, etal. 17. A New Approach for Finding Optimum Design of Electrostatic Micromotors; A. Wahab A. Salman, et al. 18. One- Cycle Controlled Boost Converter for Microsystems; N. Senouci, et al. IV: Design Methodologies. 19. Design for Reuse: HDL Based Graphic Design Entry for Parametrizable and Configurable Modules (a Case Study); A. Boszko. 20. Hierarchical Test Generation for Digital Systems; M. Brik, et al. 21. Path Selection Based on Incremental Technique; S. Cremoux, et al. 22. Chip Area Estimation for SC FIR Filter Structures in CMOS Technology; A. Dabrowski, R. Długosz. 23. Simplified Models of IC's for the Acceleration of Circuit Design; V.A. Koval, et al. 24. Low Power Methodologies for GaAs Asynchronous Systems; S.W. Lachowicz, et al. 25. Translation of C and VHDL Specifications into Interpreted Petri Nets for Hardware/Software Codesign; J. Mirkowski, Z. Skowronski. 26. FIPSOC. A Novel Mixed FPGA for System Prototyping; J.M. Moreno, et al. 27. A Nordic Project on High Speed Low Power Design in Sub-Micron CMOS Technology for Mobile Phones; O. Olesen. 28. A Reuse Concept for an I2-C-Bus Interface; M. Padeffke, W. Glauert. 29. Dynamic Analysis of Digital Circuits with 5-Valued Simulation; R. Ubar. V: Advanced Trends in Microelectronics Education. 30. A Finite State Description of the Earliest Logical Computer: The Jevons' Machine; P. Amblard. 31. Educational Computer Use in the MOS Training Fab; A. Ferreira-Noullet, et al. 32. Teaching of Analog IC Des

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