Parallel Architectures and Compilation Techniques: Proceedings of the IFIP Wg10.3 Working Conference on Parallel Architectures and Compilation Techniques, Pact '94, Montreal, Canada, 24-26 August, 1994

Parallel Architectures and Compilation Techniques: Proceedings of the IFIP Wg10.3 Working Conference on Parallel Architectures and Compilation Techniques, Pact '94, Montreal, Canada, 24-26 August, 1994

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Product Details

ISBN-13: 9780444819260
Publisher: Elsevier Science & Technology Books
Publication date: 08/28/1994
Series: IFIP Transactions Series
Pages: 374
Product dimensions: 6.30(w) x 9.45(h) x (d)

Table of Contents

Preface. Programme Committee. List of Referees. High-Performance Architectures. EM-C: programming with explicit parallelism and locality for EM-4 multiprocessor (M. Sato, Y. Kodama, S. Sakai, Y. Yamaguchi). A fine-grain threaded abstract machine (J. Vasell). Tradeoffs in the design of single chip multiprocessors (D.H. Albonesi, I. Koren). Code Generation for Multithreaded and Dataflow Architectures. An evaluation of optimized threaded code generation (L. Roh, W.A. Najjar, B. Shankar, A.P.W. Böhm). Functional I-structure, and M-structure implementations of NAS Benchmark FT (S. Sur, A.P.W. Böhm). The plan-do style compilation technique for eager data transfer in thread-based execution (M. Yasugi, S. Matsuoka, A. Yonezawa). Memory and Cache Issues.. A compiler-assisted scheme for adaptive cache coherence enforcement (T.N. Nguyen, F. Mounes-Toussi, D.J. Lilja, Z. Li). The impact of cache coherence protocols on systems using fine-grain data synchronization (D.B. Glasco, B.A. Delagi, M.J. Flynn). Towards a programming environment for a computer with intelligent memory (A. Asthana, M. Cravatts, P. Krzyzanowski). Distributed Memory Machines. Communication analysis for multicomputer compilers (I. Kim, M. Wolfe). Automatic data layout using 0-1 integer programming (R. Bixby, K. Kennedy, U. Kremer). Processor tagged descriptors: a data structure for compiling for distributed-memory multicomputers (E. Su, D.J. Palermo, P. Banerjee). Multi-Level parallelism. Resource spackling: a framework for integrating register allocation in local and global schedulers (D.A. Berson, R. Gupta, M.L. Soffa). An approach to combine predicated/speculative execution forprograms with unpredictable branches (M. Srinivas, A. Nicolau, V.H. Allan). A PDG-based tool and its use in analyzing program control dependences (C.J. Newburn, D.B. Noonburg, J.P. Shen). Compiling for Parallel Machines. Static analysis of barrier synchronization in explicitly parallel programs (T.E. Jeremiassen, S.J. Eggers). Exploiting the parallelism exposed by partial evaluation (R. Surati, A.A. Berlin). Effects of loop fusion and statement migration on the speedup of vector multiprocessors (M. Al-Mouhamed, L. Bic). Logic Languages. Practical static mode analyses of concurrent logic languages (E. Tick). Demand-driven dataflow for concurrent committed-choice code (B. Massey, E. Tick). Exploitation of fine-grain parallelism in logic languages on massively parallel architectures (H. Kim, J.-L. Gaudiot). Application Specific Architectures. From SIGNAL to fine-grain parallel implementations (O. Maffeis, P. Le Guernic). Microcode generation for flexible parallel target architectures (R. Leupers, W. Schenk, P. Marwedel). A fleng compiler for PIE64 (H. Nakada, T. Araki, H. Koike, H. Tanaka). Functional Languages, Dataflow Models and Implementation. Compiling higher-order functions for tagged-dataflow (R. Rondogiannis, W.W. Wadge). Dataflow-based lenient implementation of a functional language, valid, on conventional multi-processors (S. Kusakabe, E. Takahashi, R.-i. Taniguchi, M. Amamiya). Dataflow and logicflow models for defining a parallel prolog abstract machine (P. Kacsuk). Towards a computational model for UFO (J. Sargeant, C. Kirkham, S. Anderson). Short Papers. Software pipelining: a genetic algorithm approach (V.H. Allan, M.R. O'Neill). Parallel compilation on associative computers (C.R. Asthagiri, J.L. Potter). Partitioning of variables for multiple-register-file architectures via hypergraph coloring (A. Capitanio, N. Dutt, A. Nicolau). Realizing parallel reduction operations in Sisal 1.2 (S.M. Denton, J.T. Feo, P.J. Miller). An introduction to simplex scheduling (B. Dupont de Dinechin). Speculative evaluation for parallel graph reduction (J.S. Mattson Jr., W.G. Griswoldd). Toward a general-purpose multi-stream system (A. Mendelson, B. Mendelson). Representing control flow behaviour of programs (C. Meurillon, C. O'Donnell). Transformations on doubly nested loops (R. Sass, M. Mutka). A comparative study of data-flow architectures (D.F. Snelling, G.K. Egan). Progress report on porting Sisal to the EM-4 multiprocessor (A. Sohn, L. Kong, M. Sato). Static vs. dynamic strategies for fine-grain dataflow synchronization (J. Vasell). Trace software pipelining: a novel technique for parallelization of loops with branches (J. Wang, A. Krall, M.A. Ertl, C. Eisenbeis).

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