ISBN-10:
1881609081
ISBN-13:
9781881609087
Pub. Date:
11/01/1994
Publisher:
Mindshare Press
PCI System Architecture / Edition 2

PCI System Architecture / Edition 2

by Tom Shanley, Don Anderson

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Overview

PCI System Architecture / Edition 2

"One of the major benefits of the PCI specification is that it is defined with many engineering disciplines in mind: architecture, protocol, components, board layout, and software. Mindshare's PCI System Architecture is an excellent resource for understanding all these aspects and their interrelationships."

-Todd Koelling, Applications Engineer, Intel Corporation; member of the PCI development team PCI System Architecture describes revision 2.1 of the Peripheral Component Interconnect (PCI) bus specification, providing a clear, concise explanation of PCI's relationship to the rest of the system. This book has been updated and revised to include in-depth treatment of PCI to PCI bridges, the PCI BIOS, the 66MHz PCI bus, and more. PCI experts Tom Shanley and Don Anderson provide a comprehensive treatment of the bus including:

reflected-wave switching shared resource acquisition signal groups 64-bit extension bus arbitration add-in cards and connectors command set configuration read and write transfers expansion ROMs premature transaction termination cacheable memory support.

This book also examines the VLSI Technology VL82C59x chipset to illustrate an example PCI bus implementation.

If you design or test hardware or software that involves the PCI bus, PCI System Architecture is an essential, time-saving tool.

The PCI System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmer's perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification.

Product Details

ISBN-13: 9781881609087
Publisher: Mindshare Press
Publication date: 11/01/1994
Series: PC System Architecture Ser. , #4
Edition description: 2nd ed
Pages: 352
Product dimensions: 6.00(w) x 1.25(h) x 9.00(d)

About the Author

Mindshare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq.

Tom Shanley is one of the world's foremost authorities on PC system architecture and has personally trained thousands of engineers in hardware and software design.

Don Anderson, author and co-author of many MindShare books, passes on his wealth of experience in digital electronics and computer design by training engineers, programmers, and technicians for MindShare.

Table of Contents

About This Book
The MindShare Architecture Series
Organization of This Book
Designation of Specification Changes
Cautionary Note
Who This Book Is For
Prerequisite Knowledge
Object Size Designations
Documentation Conventions
Hex Notation
Binary Notation
Decimal Notation
Signal Name Representation
Identification of Bit Fields (Logical Groups of Bits or Signals)
We Want Your Feedback

1: Intro to PCI
PCI Bus History
PCI Bus Features
PCI Device vs
Function
Specifications Book Is Based On
Obtaining PCI Bus Specification(s)

2: Intro to PCI Bus Operation
Burst Transfer
Initiator, Target and Agents
Single- Vs
Multi-Function PCI Devices
PCI Bus Clock
Address Phase
Claiming the Transaction
Data Phase(s)
Transaction Duration
Transaction Completion and Return of Bus to Idle State
Response to Illegal Behavior
"Green" Machine

3: Intro to Reflected-Wave Switching
Each Trace Is a Transmission Line
Old Method: Incident-Wave Switching
PCI Method: Reflected-Wave Switching
CLK Signal
RST#/REQ64# Timing
Slower Clock Permits Longer Bus

4: The Signal Groups
Introduction
System Signals
PCI Clock Signal (CLK)
CLKRUN# Signal
Description
Achieving CLKRUN# Benefit on Add-In Cards
Reset Signal (RST#)
Address/Data Bus, Command Bus, and Byte Enables
Preventing Excessive Current Drain
Transaction Control Signals
Arbitration Signals
Interrupt Request Signals
Error Reporting Signals
Data Parity Error
System Error
Cache Support (Snoop Result) Signals
64-Bit Extension Signals
Resource Locking
JTAG/Boundary Scan Signals
Interrupt Request Pins
PME# and 3
3 Vaux
Sideband Signals
Signal Types
Device Cannot Simultaneously Drive and Receive a Signal
Central Resource Functions
Subtractive Decode (by ISA Bridge)
Background
Tuning Subtractive Decoder
Reading Timing Diagrams

5: PCI Bus Arbitration
Arbiter
Arbitration Algorithm
Example Arbiter with Fairness
Master Wishes to Perform More Than One Transaction
Hidden Bus Arbitration
Bus Parking
Request/Grant Timing
Example of Arbitration Between Two Masters
State of REQ# and GNT# During RST#
Pullups on REQ# From Add-In Connectors
Broken Master

6: Master and Target Latency
Mandatory Delay Before First Transaction Initiated
Bus Access Latency
Pre-2
1 Devices Can Be Bad Boys
Preventing Master from Monopolizing the Bus
Master Must Transfer Data within 8 CLKs
IRDY# Deasserted in Clock After Last Data Transfer
Latency Timer Keeps Master From Monopolizing Bus
Location and Purpose of Master Latency Timer
How LT Works
Is Implementation of LT Register Mandatory? Can LT Value Be Hardwired? How Does Software Determine Timeslice to Be Allocated to Master? Treatment of Memory Write and Invalidate Command
Preventing Target From Monopolizing Bus
General
Target Must Transfer Data Expeditiously
General
The First Data Phase Rule
General
Master's Response to Retry
Sometimes Target Can't Transfer First Data within 16 CLKs
Target Frequently Can't Transfer First Data within 16 CLKs
Two Exceptions to First Data Phase Rule
Subsequent Data Phase Rule
General
In Data Phase and Cannot Transfer Data within 8 Clocks
OK in This Data Phase, but Can't Meet Rule in Next One
Master's Response to a Disconnect
Target's Subsequent Latency and Master's Latency Timer
Target Latency During Initialization Time
Initialization Time vs
Run Time
Definition of Initialization Time and Behavior (Before 2
2)
Definition of Initialization Time and Behavior (2
2)
Delayed Transactions
The Problem
The Solution
Information Memorized
Master and Target Actions During Delayed Transaction
Commands That Can Use Delayed Transactions
Request Not Completed and Targeted Again
Special Cycle Monitoring While Processing Request
Discard of Delayed Requests
Multiple Delayed Requests from Same Master
Request Queuing in Target
Discard of Delayed Completions
Read From Prefetchable Memory
Master Tardy in Repeating Transaction
Reporting Discard of Data on a Read
Handling Multiple Data Phases
Master or Target Abort Handling
What Is Prefetchable Memory? Delayed Read Prefetch
Posting Improves Memory Write Performance
General
Combining
Byte Merging
Collapsing Is Forbidden
Memory Write Maximum Completion Limit
Transaction Ordering and Deadlocks

7: The Commands
Introduction
Interrupt Acknowledge Command
Introduction
Background
Host/PCI Bridge Handling of Interrupt Acknowledge
PCI Interrupt Acknowledge Transaction
PowerPC PReP Handling of INTR
Special Cycle Command
General
Special Cycle Generation Under Software Control
Special Cycle Transaction
Single-Data Phase Special Cycle Transaction
Multiple Data Phase Special Cycle Transaction
IO Read and Write Commands
Accessing Memory
Target Support For Bulk Commands Is Optional
Cache Line Size Register And the Bulk Commands
Bulk Commands Are Optional Performance Enhancement Tools
Bridges Must Discard Prefetched Data Not Consumed By Master
Writing Memory
Memory Write Command
Memory Write-and-Invalidate Command
Problem
Description of Memory Write-and-Invalidate Command
More Information on Memory Transfers
Configuration Read and Write Commands
Dual-Address Cycle
Reserved Bus Commands

8: Read Transfers
Some Basic Rules For Both Reads and Writes
Parity
Example Single Data Phase Read
Example Burst Read
Treatment of Byte Enables During Read or Write
Byte Enables Presented on Entry to Data Phase
Byte Enables May Change in Each Data Phase
Data Phase with No Byte Enables Asserted
Target with Limited Byte Enable Support
Rule for Sampling of Byte Enables
Cases Where Byte Enables Can Be Ignored
Performance During Read Transactions

9: Write Transfers
Example Single Data Phase Write Transaction
Example Burst Write Transaction
Performance During Write Transactions

10: Memory and IO Addressing
Memory Addressing
The Start Address
Addressing Sequence During Memory Burst
Linear (Sequential) Mode
Cache Line Wrap Mode
When Target Doesn't Support Setting on AD1:0
PCI IO Addressing
Do Not Merge Processor IO Writes
General
Decode By Device That Owns Entire IO Dword
Decode by Device with 8-Bit or 16-Bit Ports
Unsupported Byte Enable Combination Results in Target Abort
Null First Data Phase Is Legal
IO Address Management
X86 Processor Cannot Perform IO Burst
Burst IO Address Counter Management
When IO Target Doesn't Support Multi-Data Phase Transactions
Legacy IO Decode
When Legacy IO Device Owns Entire Dword
When Legacy IO Device Doesn't Own Entire Dword

11: Fast Back-to-Back & Stepping
Fast Back-to-Back Transactions
Decision to Implement Fast Back-to-Back Capability
Scenario 1: Master Guarantees Lack of Contention
1st Must Be Write, 2nd Is Read or Write, But Same Target
How Collision Avoided on Signals Driven By Target
How Targets Recognize New Transaction Has Begun
Fast Back-to-Back and Master Abort
Scenario Two: Targets Guarantee Lack of Contention
Address/Data Stepping
Advantages: Diminished Current Drain and Crosstalk
Why Targets Don't Latch Address During Stepping Process
Data Stepping
How Device Indicates Ability to Use Stepping
Designer May Step Address, Data, PAR (and PAR64) and IDSEL
Continuous and Discrete Stepping
Disadvantages of Stepping
Preemption While Stepping in Progress
Broken Master
Stepping Example
When Not to Use Stepping
Who Must Support Stepping?

12: Early Transaction End
Introduction
Master-Initiated Termination
Master Preempted
Introduction
Preemption During Timeslice
Timeslice Expiration Followed by Preemption
Master Abort: Target Doesn't Claim Transaction
Introduction
Addressing Non-Existent Device

Index

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