PowerPC Architecture: A Specification for a New Family of RISC Processors

PowerPC Architecture: A Specification for a New Family of RISC Processors

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Overview

PowerPC Architecture: A Specification for a New Family of RISC Processors by Cathy May, Ed Sikha, Rick Simpson, Cathy May

This is the official technical description of the PowerPC architecture and its hardware conventions, developed jointly by IBM, Motorola, and Apple. The book is an essential reference for hardware and system-software designers and applications programmers developing a range of products using implementations of the PowerPC family of microprocessors-from palmtops to teraFLOPS.

The PowerPC architecture provides a stable base for software, allowing applications that run on one PowerPC processor to run consistently on any other PowerPC processor. In addition, well-designed operating systems can be moved from one processor implementation to another by making only a few minor changes.

To achieve this, the specification of the architecture has been structured into three Books, corresponding to a distinct level of the architecture:

  • Book I, User Instruction Set Architecture, describes the registers, instructions, storage model, and execution model that are available to all application programs.
  • Book II, Virtual Environment Architecture, describes features of the architecture that permit application programs to create or modify code, to share data among programs in a multiprocessing system, and to optimize the performance of storage accesses.
  • Book III, Operating Environment Architecture, describes features of the architecture that permit operating systems to allocate and manage storage, to handle errors encountered by application programs, to support I/O devices, and to provide the other services expected of secure, modern multiprocessor operating systems.

      An important feature of these specifications is that they only constrain implementations on matters that affect software compatibility. Even more significant, they specify the architecture in a manner that is independent of implementation.

      The PowerPC Architecture is a must for anyone who needs to understand the levels of compatibility between different processors in the PowerPC family-the 601 microprocessor, the 603 (low-end, battery-powered requirements), 604 (optimized price/performance for scaleable symmetric multiprocessors), and the 620 (for high-end technical and commercial requirements about performance).

Product Details

ISBN-13: 9781558603165
Publisher: Elsevier Science & Technology Books
Publication date: 11/15/1993
Edition description: 2nd ed
Pages: 518
Product dimensions: 7.48(w) x 9.45(h) x (d)

Table of Contents

The PowerPC Architecture: A Specification for a New Family of RISC Processors
by International Business Machines, Inc.
    Foreword
    List of Figures
    List of Tables
    Preface
    Book I PowerPC User Instruction Set Architecture
    Book I Chapter 1 Introduction
      1.1 Overview
      1.2 Computation Modes
        1.2.1 64-bit Implementations
        1.2.2 32-bit Implementations
      1.3 Instruction Mnemonics and Operands
      1.4 Compatibility with the POWER Architecture
      1.5 Document Conventions
        1.51 Definitions and Notation
        1.5.2 Reserved Fields
        1.5.3 Description of Instruction Operations
      1.6 Processor Overview
      1.7 Instruction Formats
        1.7.1 Instruction Fields
      1.8 Classes of Instructions
        1.8.1 Defined Instruction Class
        1.8.2 Illegal Instruction Class
        1.8.3 Reserved Instruction Class
      1.9 Forms of Defined Instructions
        1.9.1 Preferred Instruction Forms
        1.9.2 Invalid Instruction Forms
        1.9.3 Optional Instructions
      1.10 Exceptions
      1.11 Storage Addressing
        1.11.1 Storage Operands
        1.11.2 Effective Address Calculation

    Book I Chapter 2 Branch Processor
      2.1 Branch Processor Overview
      2.2 Instruction Fetching
      2.3 Branch Processor Registers
        2.3.1 Condition Register
        2.3.2 Link Register
        2.3.3 Count Register
      2.4 Branch Processor Instructions
        2.4.1 Branch Instructions
        2.4.2 System Call Instruction
        2.4.3 Condition Register Logical Instructions
        2.4.4 Condition Register Field Instruction

    Book I Chapter 3 Fixed-Point Processor
      3.1 Fixed Point Processor Overview
      3.2 Fixed-Point Processor Registers
        3.2.1 General Purpose Registers
        3.2.2 Fixed-Point Exception Register
      3.3 Fixed-Point Processor Instructions
        3.3.1 Storage Access Instructions
        3.3.2 Fixed-Point Load Instructions
        3.3.3 Fixed-Point Store Instructions
        3.3.4 Fixed-Point Load and Store with Byte Reversal Instructions
        3.3.5 Fixed-Point Load and Store Multiple Instructions
        3.3.6 Fixed-Point Move Assist Instructions
        3.3.7 Storage Synchronization Instructions
        3.3.8 Other Fixed-Point Instructions
        3.3.9 Fixed-Point Arithmetic Instructions
        3.3.10 Fixed-Point Compare Instructions
        3.3.11 Fixed Point Trap Instructions
        3.3.12 Fixed-Point Logical Instructions
        3.3.13 Fixed Point Rotate and Shift Instructions
        3.3.14 Move to/from System Register Instructions

    Book I Chapter 4 Floating-Point Processor
      4.1 Floating-Point Processor Overview
      4.2 Floating-Point Processor Registers
        4.2.1 Floating-Point Registers
        4.2.2 Floating-Point Status and Control Register
      4.3 Floating-Point Data
        4.3.1 Data Format
        4.3.2 Value Representation
        4.3.3 Sign of Result
        4.3.4 Normalization and Denormalization
        4.3.5 Data Handling and Precision
        4.3.6 Rounding
      4.4 Floating-Point Exceptions
        4.4.1 Invalid Operation Exception
        4.4.2 Zero Divide Exception
        4.4.3 Overflow Exception
        4.4.4 Underflow Exception
        4.4.5 Inexact Exception
      4.5 Floating-Point Execution Models
        4.5.1 Execution Model for IEEE Operations
        4.5.2 Execution Model for Multiply-Add Type Instructions
      4.6 Floating-Point Processor Instructions
        4.6.1 Floating-Point Storage Access Instructions
        4.6.2 Floating-Point Load Instructions
        4.6.3 Floating-Point Store Instructions
        4.6.4 Floating-Point Move Instructions
        4.6.5 Floating-Point Arithmetic Instructions
        4.6.6 Floating-Point Rounding and Conversion Instructions
        4.6.7 Floating-Point Compare Instructions
        4.6.8 Floating-Point Status and Control Register Instructions

    Book I Appendix A Optional Instructions
      A.1 Floating-Point Processor Instructions
        A.1.1 Floating Point Store Instruction
        A.1.2 Floating-Point Arithmetic Instructions
        A.1.3 Floating-Point Select Instruction

    Book I Appendix B Suggested Floating-Point Models
      B.1 Floating-Point Round to Single-Precision Model
      B.2 Floating-Point Convert to Integer Model
      B.3 Floating-Point Convert from Integer Model

    Book I Appendix C Assembler Extended Mnemonics
      C.1 Symbols
      C.2 Branch Mnemonics
        C.2.1 BO and BI Fields
        C.2.2 Simple Branch Mnemonics
        C.2.3 Branch Mnemonics Incorporating Conditions
        C.2.4 Branch Prediction
      C.3 Condition Register Logical Mnemonics
      C.4 Subtract Mnemonics
        C.4.1 Subtract Immediate
        C.4.2 Subtract
      C.5 Compare Mnemonics
        C.5.1 Doubleword Comparisons
        C.5.2 Word Comparisons
      C.6 Trap Mnemonics
      C.7 Rotate and Shift Mnemonics
        C.7.1 Operations on Doublewords
        C.7.2 Operations on Words
      C.8 Move To/From Special Purpose Register Mnemonics
      C.9 Miscellaneous Mnemonics

    Book I Appendix D Little-Endian Byte Ordering
      D.1 Byte Ordering
      D.2 Strict Mapping Examples
        D.2.1 Big-Endian mapping
        D.2.2 Little-Endian Mapping
      D.3 PowerPC Byte Ordering
        D.3.1 Controlling PowerPC Byte Ordering
        D.3.2 PowerPC Little-Endian Byte Ordering
      D.4 PowerPC Data Storage Addressing in Little-Edian Mode
        D.4.1 Individual Aligned Scalars
        D.4.2 Other Scalars
        D.4.3 Segment Tables and Page Tables
      D.5 PowerPC Instruction Storage Addressing in Little-Endian Mode
      D.6 PowerPC Cache Management and Lookaside Buffer Management Instruction in Little-Endian Mode
      D.7 PowerPC I/O in Little-Endian Mode
      D.8 Origin of Endian

    Book I Appendix E Cross-Reference for Changed POWER Mnemonics
      E.1 Synchronization
        E.1.1 Synchronization Primitives
        E.1.2 Lock Acquisition and Release
        E.1.3 List Insertion
        E.1.4 Notes
      E.2 Multiple-Precision Shifts
      E.3 Floating-Point Conversions
        E.3.1 Conversion from Floating Number to Floating-Point Integer
        E.3.2 Conversion from Floating-Point Number to Signed Fixed Point Integer Doubleword
        E.3.3 Conversion from Floating-Point Number to Unsigned Fixed-Point Integer Doubleword
        E.3.4 Conversion from Floating-Point Number to Signed Fixed-Point Integer Word
        E.3.5 Conversion from Floating-Point Number to Unsigned Fixed Point Integer Word
        E.3.6 Conversion from Signed Fixed-Point Integer Doubleword to Floating-Point Number
        E.3.7 Conversion from Unsigned Fixed-Point Integer Doubleword to Floating-Point Number
        E.3.8 Conversion from Signed Fixed-Point Integer Word to Floating-Point Number
        E.3.9 Conversion from Unsigned Fixed-Point Integer Word to Floating-Point Number
      E.4 Floating-Point Selection
        E.4.1 Comparison to Zero
        E.4.2 Minimum and Maximum
        E.4.3 Simple if-then-else Constructions
        E.4.4 Notes

    Book I Appendix F Cross-Reference for Changed POWER Mnemonics
    Book I Appendix G Incompatibilities with the POWER Architecture
      G.1 New Instructions, Formerly Privileged Instructions
      G.2 Newly Privileged Instructions
      G.3 Reserved Bits in Instructions
      G.4 Reserved Bits in Registers
      G.5 Alignment Check
      G.6 Condition Register
      G.7 Inappropriate use of LK and Rc Bits
      G.8 BO Field
      G.9 Branch Conditional to Count Register
      G.10 System Call
      G.11 Fixed-Point Exception Register (XER)
      G.12 Update Forms of Storage Access
      G.13 Multiple Register Loads
      G.14 Alignment for Load/Store Multiple
      G.15 Move Assist Instructions
      G.16 Synchronization
      G.17 Move T/From SPR
      G.18 Effects of Exceptions on FPSCR Bits FR and FI
      G.19 Floating-Point Store Instructions
      G.20 Move from FPSCR
      G.21 Zeroing Bytes in the Data Cache
      G.22 Floating-Point Load/Store to Direct-Store Segment
      G.23 Segment Register Instructions
      G.24 TLB Entry Invalidation
      G.25 Floating-Point Interrupts
      G.26 Timing Facilities
      G.27 Deleted Instructions
      G.28 Discontinued Opcodes
      G.29 POWER2 Compatibility
        G.29.1 Cross-Reference for Changed POWER2 Mnemonics
        G.29.2 Floating-Point Conversion to Integer
        G.29.3 Storage Ordering
        G.29.4 Floating-Point Interrupts
        G.29.5 Trace Interrupts
        G.29.6 Deleted Instructions
        G.29.7 Discontinued Opcodes

    Book I Appendix H New Instructions
      H.1 New Instructions for All Implementations
      H.2 New Instructions for 64-Bit Implementations Only
      H.3 New Instructions for 32-Bit Implementations Only

    Book I Appendix I Illegal Instructions
    Book I Appendix J Reserved Instructions
    Book I Appendix K PowerPC Instruction Set Sorted by Opcode
    Book I Appendix L PowerPC Instruction Set Sorted by Mnemonic
    Book II PowerPC Virtual Environment Architecture
    Book II Chapter 1 Storage Model
      1.1 Definitions and Notation
      1.2 Introduction
      1.3 Virtual Storage
      1.4 Single-Copy Atomicity
      1.5 Memory Coherence
        1.5.1 Coherence Required
        1.5.2 Coherence Not Required
      1.6 Storage Control Attributes
      1.7 Cache Models
        1.7.1 Split or Dual Caches
        1.7.2 Combined Cache
        1.7.3 Write Through Data Cache
      1.8 Shared Storage
        1.8.1 Storage Access Ordering
        1.8.2 Atomic Update Primitives

    Book II Chapter 2 Effect of Operand Placement on Performance
      2.1 Instruction Restart
      2.2 Atomicity and Order

    Book II Chapter 3 Storage Cont

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