This work will educate chip and system designers on a method for accurately predicting circuit and system reliability in order to estimate failures that will occur in the field as a function of operating conditions at the chip level. This book will combine the knowledge taught in many reliability publications and illustrate how to use the knowledge presented by the semiconductor manufacturing companies in combination with the HTOL end-of-life testing that is currently performed by the chip suppliers as part of their standard qualification procedure and make accurate reliability predictions. This book will allow chip designers to predict FIT and DPPM values as a function of operating conditions and chip temperature so that users ultimately will have control of reliability in their design so the reliability and performance will be considered concurrently with their design.
- The ability to include reliability calculations and test results in their product design
- The ability to use reliability data provided to them by their suppliers to make meaningful reliability predictions
- Have accurate failure rate calculations for calculating warrantee period replacement costs
|Product dimensions:||5.90(w) x 8.80(h) x 0.40(d)|
About the Author
Joseph B. Bernstein is Professor of Electrical Engineering at Ariel University, Ariel, Israel. He received his PhD from MIT, Cambridge, MA, USA, and has previously worked as a Professor at Bar Ilan University, Israel, and at the University of Maryland and the MIT Lincoln Laboratory. He has co-authored two books.
Table of ContentsIntroduction
1. Shortcut to accurate reliability prediction
2. M-HTOL Principles
3. Failure Mechanisms
4. New M-HTOL Approach