This book is intended as an innovative overview of current formal verification methods, combined with an in-depth analysis of some advanced techniques to improve the scalability of these methods, and close the gap between design and verification in computer-aided design. Formal Verification: Scalable Hardware Verification with Symbolic Simulation explains current formal verification methods and provides an in-depth analysis of some advanced techniques to improve the scalability of these methods and close the gap between design and verification in computer-aided design. It provides the theoretical background required to present such methods and advanced techniques, i.e. Boolean function representations, models of sequential networks and, in particular, some novel algorithms to expose the disjoint support decompositions of Boolean functions, used in one of the scalable approaches.
|Edition description:||Softcover reprint of hardcover 1st ed. 2006|
|Product dimensions:||6.10(w) x 9.25(h) x 0.02(d)|
Table of ContentsDesign and Verification of Digital Systems.- Symbolic Simulation.- Compacting Intermediate States.- Approximate Simulation.- Exact Parametrizations.- Conclusion.