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Semiconductor Memories: Technology, Testing, and Reliability / Edition 1

Semiconductor Memories: Technology, Testing, and Reliability / Edition 1

by Ashok K. Sharma, MD Facp Sharma, IEEEAshok K. Sharma


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Semiconductor Memories provides in-depth coverage in the areas of design for testing, fault tolerance, failure modes and mechanisms, and screening and qualification methods including.
* Memory cell structures and fabrication technologies.
* Application-specific memories and architectures.
* Memory design, fault modeling and test algorithms, limitations, and trade-offs.
* Space environment, radiation hardening process and design techniques, and radiation testing.
* Memory stacks and multichip modules for gigabyte storage.

Product Details

ISBN-13: 9780780310001
Publisher: Wiley
Publication date: 09/09/2002
Pages: 480
Product dimensions: 7.20(w) x 10.10(h) x 1.30(d)

About the Author

ASHOK K. SHARMA is the author of Semiconductor Memories: Technology, Testing, and Reliability. He is currently working as a reliability engineering manager at NASA, Goddard Space Flight Center, Greenbelt, Maryland.

Read an Excerpt

Semiconductor Memories

Technology, Testing, and Reliability
By Ashok K. Sharma

John Wiley & Sons

ISBN: 0-7803-1000-4

Chapter One


Semiconductor memories are usually considered to be the most vital microelectronic component of digital logic system design, such as computers and microprocessor-based applications ranging from satellites to consumer electronics. Therefore, advances in the fabrication of semiconductor memories including process enhancements and technology developments through the scaling for higher densities and faster speeds help establish performance standards for other digital logic families. Semiconductor memory devices are characterized as volatile random access memories (RAMs), or nonvolatile memory devices. In RAMs, the logic information is stored either by setting up the logic state of a bistable flip-flop such as in a static random access memory (SRAM), or through the charging of a capacitor as in a dynamic random access memory (DRAM). In either case, the data are stored and can be read out as long as the power is applied, and are lost when the power is turned off; hence, they are called volatile memories.

Nonvolatile memories are capable of storing the data, even with the power turned off. The nonvolatile memory data storage mode may be permanent or reprogrammable, depending upon the fabrication technology used. Nonvolatile memories are used for program and microcode storage in a wide variety of applications in the computer, avionics, telecommunications, and consumer electronics industries. A combination of single-chip volatile as well as nonvolatile memory storage modes is also available in devices such as nonvolatile SRAM (nvRAM) for use in systems that require fast, reprogrammable nonvolatile memory. In addition, dozens of special memory architectures have evolved which contain some additional logic circuitry to optimize their performance for application-specific tasks.

This book on semiconductor memories covers random access memory technologies (SRAMs and DRAMs) and their application-specific architectures; nonvolatile memory technologies such as read-only memories (ROMs), programmable read-only memories (PROMs), and erasable and programmable read-only memories (EPROMs) in both ultraviolet erasable (UVPROM) and electrically erasable (EEPROM) versions; memory fault modeling and testing; memory design for testability and fault tolerance; semiconductor memory reliability; semiconductor memory radiation effects; advanced memory technologies; and high-density memory packaging technologies.

Chapter 2 on "Random Access Memory Technologies," reviews the static and dynamic RAM technologies as well as their application-specific architectures. In the last two decades of semiconductor memory growth, the DRAMs have been the largest volume volatile memory produced for use as main computer memories because of their high density and low cost per bit advantage. SRAM densities have generally lagged a generation behind the DRAMs, i.e., the SRAMs have about one-fourth the capacity of DRAMs, and therefore tend to cost about four times per bit as the DRAMs. However, the SRAMs offer low-power consumption and high-performance features which make them practical alternatives to the DRAMs. Nowadays, a vast majority of SRAMs are being fabricated in the NMOS and CMOS technologies, and a combination of two technologies (also referred to as the mixed-MOS) for commodity SRAMs.

Bipolar memories using emitter-coupled logic (ECL) provide very fast access times, but consume two-three times more power than MOS RAMs. Therefore, in high-density and high-speed applications, various combinations of bipolar and MOS technologies are being used. In addition to the MOS and bipolar memories referred to as the "bulk silicon" technologies, silicon-on-insulator (SOI) isolation technology such as silicon-on-sapphire (SOS) SRAMs have been developed for improved radiation hardness. The SRAM density and performance are usually enhanced by scaling down the device geometries. Advanced SRAM designs and architectures for 4 and 16 Mb density chips with submicron feature sizes (e.g., 0.2-0.6 jxm) are reviewed. Application-specific memory designs include first-in first-out (FIFO), which is an example of shift register memory architecture through which the data are transferred in and out serially. The dual-port RAMs allow two independent devices to have simultaneous read and write access to the same memory. Special nonvolatile, byte-wide RAM configurations require not only very low operating power, but have battery back-up dataretention capabilities. The content-addressable memories (CAMs) are designed and used both as the embedded modules on larger VLSI chips and as stand-alone memory for specific system applications.

The DRAMs store binary data in cells on capacitors in the form of charge which has to be periodically refreshed in order to prevent it from leaking away. A significant improvement in DRAM evolution has been the switch from three-transistor (3-T) designs to one-transistor (1-T) cell design that has enabled production of 4 and 16 Mb density chips that use advanced, 3-D trench capacitor and stacked capacitor cell structures. DRAMs of 64 Mb density have been sampled, and prototypes for 256 Mb are in development. The DRAMs are susceptible to soft errors (or cell logic upset) occurring from alpha particles produced by trace radioactive packaging material. In NMOS/CMOS DRAM designs, various techniques are used to reduce their susceptibility to the soft-error phenomenon. The BiCMOS DRAMs have certain advantages over the pure CMOS designs, particularly in access time. The technical advances in multimegabit DRAMs have resulted in greater demand for application-specific products such as the pseudostatic DRAM (PSRAM) which uses dynamic storage cells but contains all refresh logic onchip that enables it to function similarly to a SRAM. Video DRAMs (VDRAMs) have been produced for use as the multiport graphic buffers. A high-speed DRAM (HSDRAM) has been developed with random access time approaching that of SRAMs while retaining the density advantage of 1-T DRAM design. Some other examples of high-speed DRAM innovative architectures are synchronous, cached, and Rambus DRAMs.

Chapter 3 reviews various nonvolatile memory (NVM) technologies. A category of NVM is read-only memories (ROMs) in which the data are written permanently during manufacturing, or the user-programmable PROMs in which the data can be written only once. The PROMs are available in both bipolar and CMOS technologies. In 1970, a floating polysilicon-gate-based erasable programmable read-only memory was developed in which hot electrons are injected into the floating gate and removed either by ultraviolet internal photoemission or Fowler-Nordheim tunneling. The EPROMs (also known as UVEPROMs) are erased by removing them from the target system and exposing them to ultraviolet light. Since an EPROM consists of single-transistor cells, they can be made in densities comparable to the DRAMs. Floating-gate avalanche-injection MOS transistors (FAMOS) theory and charge-transfer mechanisms are discussed. Several technology advances in cell structures, scaling, and process enhancements have made possible the fabrication of 4-16 Mb density EPROMs. A cost-effective alternative has been the one-time programmable (OTP) EPROM introduced by the manufacturers for the high-volume applications ROM market.

An alternative to EPROM (or UYEPROM) has been the development of electrically erasable PROMs (EEPROMs) which offer in-circuit programming flexibility. The several variations of this technology include metal-nitride-oxide-semiconductor (MNOS), silicon-oxide-nitrideoxide-semiconductor (SONOS), floating-gate tunneling oxide (FLOTOX), and textured polysilicon. Since the FLOTOX is the most commonly used EEPROM technology, the Fowler- Nordheim tunneling theory for a FLOTOX transistor operation is reviewed. The conventional, frill functional EEPROMs have several advantages, including the byte-erase, byte-program, and random access read capabilities. The conventional EEPROMs used NOR-gate cells, but the modified versions include the NAND-structured cells that have been used to build 5 V-only 4 Mb EEPROMs. An interesting NVM architecture is the nonvolatile SRAM, a combination of EEPROM and SRAM in which each SRAM cell has a corresponding "shadow" EEPROM cell. The EPROMs, including UVEPROMs and EEPROMs, are inherently radiation-susceptible. The SONOS technology EEPROMs have been developed for military and space applications that require radiation-hardened devices. Flash memories based on EPROM or EEPROM technologies are devices for which the contents of all memory array cells can be erased simultaneously through the use of an electrical erase signal. The flash memories, because of their bulk erase characteristics, are unlike the floating-gate EEPROMs which have select transistors incorporated in each cell to allow for the individual byte erasure. Therefore, the flash memories can be made roughly two or three times smaller than the floating-gate EEPROM cells. The improvements in flash EEPROM cell structures have resulted in the fabrication of 8 and 16 Mb density devices for use in high-density nonvolatile storage applications such as memory modules and memory cards.

Chapter 4 on "Memory Fault Modeling and Testing," reviews memory failure modes and mechanisms, fault modeling, and electrical testing. The memory device failures are usually represented by a bathtub curve and are typically grouped into three categories, depending upon the product's operating life cycle stage where the failures occur. Memory fault models have been developed for the stuck-at faults (SAFs), transition faults (TFs), address faults (AFs), bridging faults (BFs), coupling faults (CFs), pattern-sensitive faults (PSFs), and the dynamic (or delay) faults. A most commonly used model is the single-stuck-at fault (SSF) which is also referred to as the classical or standard fault model. However, the major shortcoming of the stuck-at fault model is that the simulation using this model is no longer an accurate quality indicator for the ICs like memory chips. A large percentage of physical faults occurring in the ICs can be considered as the bridging faults (BFs) consisting of shorts between two or more cells or lines. Another important category of faults that can cause the semiconductor RAM cell to function erroneously is the coupling or PSFs. March tests in various forms have been found to be quite effective for detecting the SAFs, TFs, and CFs. Many algorithms have been proposed for the neighborhood pattern-sensitive faults (NPSFs) based on an assumption that the memory array's physical and logical neighborhoods are identical. This may not be a valid assumption in state-of-the-art memory chips which are being designed with the spare rows and columns to increase yield and memory array reconfiguration, if needed. The embedded RAMs which are being used frequently are somewhat harder to test because of their limited observability and controllability. A defect-oriented (inductive fault) analysis has been shown to be quite useful in finding various defect mechanisms for a given layout and technology.

In general, the memory electrical testing consists of the dc and ac parametric tests and functional tests. For RAMs, various functional test algorithms have been developed for which the test time is a function of the number of memory bits (n) and range in complexity from O(n) to O([n.sup.2]). The selection of a particular set of test patterns for a given RAM is influenced by the type of failure modes to be detected, memory bit density which influences the test time, and the memory ATE availability. These are the deterministic techniques which require well-defined algorithms and memory test input patterns with corresponding measurements of expected outputs. An alternate test approach often used for the memories is random (or pseudorandom) testing which consists of applying a string of random patterns simultaneously to a device under test and to a reference memory, and comparing the outputs. Advanced megabit memory architectures are being designed with special features to reduce test time by the use of the multibit test (MBT), line mode test (LMT), and built-in self-test (BIST). The functional models for nonvolatile memories are basically derived from the RAM chip functional model, and major failure modes in the EPROMs such as the SAFs, AFs, and BFs can be detected through functional test algorithms. Recent studies have shown that monitoring of the elevated quiescent supply currents (IDDQ) appears to be a good technique for detecting the bridging failures. The IDDQ fault models are being developed with a goal to achieve 100% physical defect coverage. Application-specific memories such as the FIFOs, video RAMs, synchronous static and dynamic RAMs, and double-buffered memories (DBMs) have complex timing requirements and multiple setup modes which require a suitable mix of sophisticated test hardware, the DFT and BIST approach.

Chapter 5 reviews the memory design for testability (DFT) techniques, RAM and ROM BIST architectures, memory error-detection and correction (EDAC) techniques, and the memory fault-tolerance designs. In general, the memory testability is a function of variables such as circuit complexity and design methodology. The general guidelines for a logic design based on practical experience are called the ad hoc design techniques such as logic partitioning, and addition of some I/O test points for the embedded RAMs to increase controllability and observability. Structured design techniques are based upon a concept of providing uniform design for the latches to enhance logic controllability, and commonly used methodologies include the level-sensitive scan design (LSSD), scan path, scan/set logic, random access scan, and the boundary scan testing (BST). The RAM BIST techniques can be classified into two categories as the "on-line BIST" and "off-line BIST." The BIST is usually performed by applying certain test patterns, measuring the output response using linear feedback shift registers (LFSRs), and compressing it. The various methodologies for the BIST include exhaustive testing, pseudo-random testing, and the pseudoexhaustive testing. For the RAMs, two BIST approaches have been proposed that utilize either the random logic or a microcoded ROM. The major advantages associated with a microcoded ROM over the use of random logic are a shorter design cycle, the ability to implement alternative test algorithms with minimal changes, and ease in testability of the microcode. The RAM BIST implementation strategies include the use of the algorithmic test sequence (ATS), the 13N March algorithm with a data-retention test, a fault-syndrome-based strategy for detecting the PSFs, and the built-in logic block observation (BILBO) technique. For the embedded memories, various DFT and BIST techniques have been developed such as the scan-path-based flag-scan register (FLSR) and the random-pattern-based circular self-test path (CSTP).

Advanced BIST architectures have been implemented to allow parallel testing with on-chip test circuits that utilize multibit test (MBT) and line mode test (LMT). An example is the column address-maskable parallel test (CMT) architecture which is suitable for the ultra-high-density DRAMs. The current generation megabit memory chips include spare rows and columns (redundancies) in the memory array to compensate for the faulty cells. In addition, to improve the memory chip yield, techniques such as the built-in self-diagnosis (BISD) and built-in self-repair (BISR) have been investigated. BIST schemes for ROMs have been developed that are based on exhaustive testing and test response compaction. The conventional exhaustive test schemes for the ROMs use compaction techniques which are parity-based, count-based, or polynomial-division-based (signature analysis).


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Table of Contents


Chapter 1: Introduction.

Chapter 2: Random Access Memory Technologies.

2.1 Introduction.

2.2 Static Random Access Memories (SRAMs).

2.3 Dynamic Random Access Memories (DRAMs).

Chapter 3: Nonvolatile Memories.

3.1 Introduction.

3.2 Masked Read-Only Memories (ROMs).

3.3 Programmable Read-Only Memories (PROMs).

3.4 Erasable (UV)-Programmable Read-Only Memories (EPROMs).

3.5 Electrically Erasable PROMs (EEPROMs).

3.6 Flash Memories (EPROMs or EEPROMs).

Chapter 4: Memory Fault Modeling and Testing.

4.1 Introduction . . . .

4.2 RAM Fault Modeling.

4.3 RAM Electrical Testing.

4.4 RAM Pseudorandom Testing.

4.5 Megabit DRAM Testing.

4.6 Nonvolatile Memory Modeling and Testing.

4.7 IDDQ Fault Modeling and Testing.

4.8 Application Specific Memory Testing.

Chapter 5: Memory Design for Testability and Fault Tolerance.

5.1 General Design for Testability Techniques.

5.2 RAM Built-in Self-Test (BIST).

5.3 Embedded Memory DFT and BIST Techniques.

5.4 Advanced BIST and Built-in Self-Repair Architectures.

5.5 DFT and BIST for ROMs.

5.6 Memory Error-Detection and Correction Techniques.

5.7 Memory Fault-Tolerance Designs.

Chapter 6: Semiconductor Memory Reliability.

6.1 General Reliability Issues.

6.2 RAM Failure Modes and Mechanisms.

6.3 Nonvolatile Memory Reliability.

6.4 Reliability Modeling and Failure Rate Prediction.

6.5 Design for Reliability.

6.6 Reliability Test Structures.

6.7 Reliability Screening and Qualification.

Chapter 7: Semiconductor Memory Radiation Effects.

7.1 Introduction.

7.2 Radiation Effects.

7.3 Radiation-Hardening Techniques.

7.4 Radiation Hardness Assurance and Testing.

Chapter 8: Advanced Memory Technologies.

8.1 Introduction.

8.2 Ferroelectric Random Access Memories (FRAMs).

8.3 Gallium Arsenide (GaAs) FRAMs.

8.4 Analog Memories.

8.5 Magnetoresistive Random Access Memories (MRAMs).

8.6 Experimental Memory Devices.

Chapter 9: High-Density Memory Packaging Technologies.

9.1 Introduction.

9.2 Memory Hybrids and MCMs (2-D).

9.3 Memory Stacks and MCMs (3-D).

9.4 Memory MCM Testing and Reliability Issues.

9.5 Memory Cards.

9.6 High-Density Memory Packaging Future Directions.


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