Structured Logic Design with VHDL

Structured Logic Design with VHDL

by James Armstrong, Gail Gray

Hardcover(Older Edition)

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Product Details

ISBN-13: 9780138552060
Publisher: Prentice Hall Professional Technical Reference
Publication date: 05/28/1993
Edition description: Older Edition
Pages: 496
Product dimensions: 7.23(w) x 9.55(h) x 0.96(d)

Table of Contents

Preface xi
Structured Design Concepts
1(17)
The Abstraction Hierarchy
1(5)
Textual Vs. Pictorial Representations
6(2)
Types of Behavioral Descriptions
8(1)
Design Process
8(3)
Structural Design Decomposition
11(1)
The Digital Design Space
12(1)
Problems
13(5)
Design Tools
18(25)
CAD Tool Taxonomy
18(2)
Editors
18(1)
Simulators
19(1)
Checkers and Analyzers
20(1)
Optimizers and Synthesizers
20(1)
Schematic Editors
20(3)
Simulators
23(5)
Simulation Cycle
26(1)
Simulator Organization
26(1)
The Language Scheduling Mechanism
27(1)
Simulation Efficiency
27(1)
The Simulation System
28(2)
Simulation Aids
30(3)
Model Preparation
30(1)
Model Test Vector Development
31(1)
Model Debugging
32(1)
Results Interpretation
33(1)
Applications of Simulation
33(2)
Synthesis Tools
35(4)
Problems
39(4)
Basic Features of VHDL
43(82)
The Advent of Hardware Description Languages
43(1)
VHDL: The VHSIC Hardware Description Language
44(1)
Design Entities
45(1)
Architectural Bodies
46(4)
Model Testing
50(1)
Block Statements
51(2)
Processes
53(1)
Lexical Description
53(6)
Character Set
54(1)
Lexical Elements
54(1)
Delimiters
55(1)
Identifiers
55(1)
Comments
56(1)
Character Literal
57(1)
String Literal
57(1)
Bit String Literal
58(1)
Abstract Literal
58(1)
Decimal Literal
58(1)
Based Literal
59(1)
VHDL Source File
59(1)
Data Types
59(1)
Classification of Types
60(1)
Scalar Data Types
60(6)
Enumeration Types
60(3)
Numeric Data Types---Integer and Real
63(1)
Physical Data Types
64(2)
Composite Data Types
66(2)
Arrays
66(1)
Records
67(1)
Access Types
68(1)
File Types
68(1)
Type Marks
68(1)
Classes of Objects
69(1)
Declaration of Data Objects
69(3)
Declaration of Constants
69(1)
Declaration of Variables
70(2)
Declaration of Signals
72(1)
Assignment Statements
72(4)
Variable Assignment Statements
72(1)
Signal Assignment Statements
73(1)
Signal Drivers
74(1)
Signal Attributes
75(1)
Operators and Expressions
76(6)
Logical Operators
76(2)
Relational Operators
78(1)
Adding Operators
79(1)
Sign Operators
80(1)
Multiplying Operators
80(1)
Miscellaneous Operators
81(1)
Sequential Control Statements
82(3)
Wait Statement
82(1)
If Statement
82(1)
Case Statement
83(1)
Loop Statement
84(1)
Next Statement
84(1)
Exit Statement
85(1)
Null Statement
85(1)
Concurrent Statements
85(5)
Process Statement
85(2)
Concurrent Assert Statement
87(1)
Concurrent Signal Assignment Statement
88(2)
Functions and Procedures
90(4)
Functions
90(2)
Procedures
92(1)
Subprogram Usage Rules
92(2)
Overloading
94(2)
Packages
96(1)
Visibility
97(2)
Libraries
99(2)
Configurations
101(2)
File I/O
103(7)
Formatted I/O
104(3)
Text I/O
107(3)
The Formal Nature of VHDL
110(1)
Summary
111(2)
Problems
113(12)
Basic VHDL Modeling Techniques
125(48)
Introduction
125(1)
Propagation Delay
125(3)
Delay and Concurrency
128(2)
Sequential and Concurrent Statements in VHDL
130(1)
Implementation of Time Delay in the VHDL Simulator
131(5)
Effects of Inertial and Transport Delay on Signal Propagation
136(1)
The VHDL Scheduling Algorithm
137(3)
Waveform Updating
138(2)
Side Effects
140(1)
Modeling Combinational and Sequential Logic
140(3)
Primitives
143(1)
Combinational Logic
143(11)
Gate Primitive
143(1)
Buffer Primitive
144(1)
Adder Primitive
144(1)
Multiplexer Primitive
144(2)
Decoder Primitive
146(1)
Encoder Primitive
146(1)
Shifter Primitive
146(1)
The Data Operations Package
147(2)
ALU Model
149(2)
PLA Primitive
151(3)
Sequential Logic
154(6)
Flip-flop Primitives
154(1)
Register Primitives
154(1)
Latch Primitives
154(1)
Shift Register Primitive
155(2)
Counter Primitive
157(1)
Ram Primitive
157(2)
Oscillator Primitives
159(1)
Testing the Primitives
160(2)
Problems
162(11)
Algorithmic Level Design
173(58)
General Algorithmic Model Development in Behavioral Domain
173(18)
The Process Model Graph
174(2)
Algorithmic Model of a Parallel to Serial Converter
176(3)
Algorithmic Models with Timing
179(4)
Checking Timing
183(3)
VHDL Modeling Style for General Algorithmic Models
186(4)
A Synthesis Example
190(1)
Representation of System Interconnections
191(6)
A Comprehensive Algorithmic Modeling Example
192(5)
Algorithmic Modeling of Systems
197(1)
Multivalued Logic Systems
197(20)
Logic Package SYSTEM4
199(1)
Resolution Functions
199(3)
Sense and Drive Functions
202(1)
A Comprehensive System Example
203(3)
Hardware Interpretation of the Control Steps
206(4)
Accuracy of Wait Statement Algorithmic Model
210(1)
Resetting
211(1)
Control Sequence Benching
212(2)
Time Multiplexing
214(3)
Direct Mapping of a State Table to an Algorithmic Description
217(2)
Problems
219(12)
Register Level Design
231(24)
Transition from Algorithmic to Data Flow Descriptions
231(4)
A Transformation Example
232(3)
Timing Analysis
235(2)
Control Unit Design
237(3)
Types of Control Units
238(2)
The Ultimate RISC Machine
240(9)
The Single URISC Instruction
240(1)
URISC Architecture
241(2)
URISC Control
243(1)
The URISC Instruction Cycle Control Sequence
243(2)
URISC Timing
245(1)
A URISC System
245(1)
Design of the URISC at the Register Level
246(1)
Microcoded Controller for the URISC Processor
247(2)
Hardwired Controller for the URISC Processor
249(1)
Problems
249(6)
Detailed Gate Level Design
255(53)
Introduction
255(1)
Accurate Gate Level Modeling
255(8)
Error Checking
263(1)
Multivalued Logic for Gate Level Modeling
264(2)
System MVL7
266(1)
The MVL7 Resolution Function
267(3)
Variations on MVL7
270(1)
More Values
271(1)
A Generalized State/Strength Model
272(3)
Interval Logic
275(2)
The Vantage System
277(3)
Gate Models for Higher Valued Systems
280(1)
The Vangate Gate Model
281(5)
More Accurate Delay Modeling
286(1)
Configuration Declarations for Gate Level Models
287(3)
Use of Component Libraries
290(3)
Modeling of Races and Hazards
293(5)
Some Different Approaches to Delay Control
298(5)
Problems
303(5)
Multilevel Design
308(62)
Design of Combinational Logic Circuits
308(16)
Example 8.1: Specification for Binary Comparator (COM)
308(1)
Combinational Logic Design at Algorithmic Level
309(1)
ARRAY Model
310(2)
CASE Model
312(1)
Optimization Procedures at the Algorithm Level
312(4)
Design of Data Flow Models of Combinational Logic in the Behavioral Domain
316(1)
Decomposition
316(1)
Synthesis of Data Flow Descriptions
316(2)
Synthesis of Gate Level Structural Domain Combinational Logic Circuits
318(2)
Summary of Design Activity for Combinational Logic Circuits
320(4)
Design of Sequential Logic Circuits
324(13)
Moore or Mealy Decision
325(1)
Construction of a State Table
326
Creating a State Diagram
317(13)
Transition List Approach
330(1)
Creating a VHDL Model for State Machines
331(4)
Synthesis of VHDL State Machine Models
335(2)
Design of Microprogrammed Control Units
337(22)
Interface Between Controller and Device
337(1)
Comparison of Hardwired and Microprogrammed Control Units
338(2)
Basic Microprogrammed Control Unit
340(2)
Algorithmic Level Model of BMCU
342(3)
Synthesis of Microprogrammed Controllers for State Machines
345(6)
Generality and Limitations of Microprogrammed Control Units
351(3)
Alternative Condition Select Methods
354(3)
Alternative Branching Methods
357(2)
Problems
359(11)
Algorithmic Synthesis
370(69)
Benefits of Algorithmic Synthesis
370(2)
Algorithmic Synthesis Tasks
372(8)
Compilation of VHDL Description into an Internal Format
373(1)
Scheduling
373(1)
Allocation
374(2)
Interaction of Scheduling and Allocation
376(3)
Gantt Charts and Utilization
379(1)
Creating FSM VHDL from an Allocation Graph
380(1)
Scheduling Techniques
380(10)
Transformational Scheduling
382(1)
Iterative Constructive Scheduling
383(1)
ASAP Scheduling
384(2)
ALAP Scheduling
386(1)
List Scheduling
386(3)
Freedom-Directed Scheduling
389(1)
Allocation Techniques
390(26)
Greedy Allocation
390(1)
Allocation by Exhaustive Search
391(1)
Left Edge Algorithm
391(2)
Assigning Functional Units and Interconnection Paths
393(4)
An Analysis of the Allocation Process
397(2)
A Near Minimal Cluster Partitioning Algorithm
399(5)
Profit Directed Cluster Partitioning Algorithm
404(1)
Application of PDCPA to Register Allocation
405(3)
Application of PDCPA to Functional Unit Allocation
408(4)
Application of PDCPA to Data Path Allocation
412(3)
State of the Art in High-Level Synthesis
415(1)
Automated Synthesis of VHDL Constructs
416(11)
Constructs That Involve Selection
416(1)
Mapping Case Statements to Multiplexers
417(1)
Mapping IF... THEN... ELSE Statements to Multiplexers
418(1)
Mapping Indexed Vector References to Multiplexers
419(1)
Loop Constructs
420(5)
Functions and Procedures
425(2)
Problems
427(12)
References 439(21)
Appendix 460(19)
Index 479

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