Pub. Date:
Cambridge University Press
Testing of Digital Systems / Edition 1

Testing of Digital Systems / Edition 1

by N. K. Jha
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Product Details

ISBN-13: 2900521773569
Publisher: Cambridge University Press
Publication date: 05/28/2003
Edition description: New Edition
Pages: 1000
Product dimensions: 6.00(w) x 1.25(h) x 9.00(d)

About the Author

Niraj Jha is Professor of Electrical Engineering at Princeton University and head of the Center of Embedded System-on-a-Chip Design, where his current research is focussed on the synthesis and testing of these devices. He is a fellow of IEEE, associate editor of IEEE Transactions on VLSI Systems and The Journal of Electronic Testing: Theory and Applications (JETTA) and a recipient of the AT&T Foundation award and the NEC preceptorship award for research excellence.

Sandeep Gupta is an Associate Professor in the Department of Electrical Engineering at the University of Southern California, USA. He is Co-Director of the M.S. Program in VLSI Design, with research interests in the area of VLSI testing and design. He is a member of the IEEE.

Table of Contents

1. Introduction;
2. Fault models;
3. Combinational logic and fault simulation;
4. Test generation for combinational circuits;
5. Sequential ATPG;
6. IDDQ testing;
7. Functional testing;
8. Delay fault testing;
9. CMOS testing;
10. Fault diagnosis;
11. Design for testability;
12. Built-in self-test;
13. Synthesis for testability;
14. Memory testing;
15. High-level test synthesis;
16. System-on-a-chip testing; Index.

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