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ISBN-13: | 9780691603018 |
---|---|

Publisher: | Princeton University Press |

Publication date: | 07/14/2014 |

Series: | Princeton Legacy Library , #210 |

Edition description: | Reprint |

Pages: | 590 |

Product dimensions: | 8.00(w) x 10.00(h) x (d) |

## Read an Excerpt

#### Theory of CMOS Digital Circuits and Circuit Failures

**By Masakazu Shoji**

**PRINCETON UNIVERSITY PRESS**

**Copyright © 1992 Princeton University Press**

All rights reserved.

ISBN: 978-0-691-08763-4

All rights reserved.

ISBN: 978-0-691-08763-4

CHAPTER 1

**Physics of CMOS Integrated Circuits**

**1.1 Introduction**

In this chapter we prepare the background materials for this book—concepts and methods necessary for detailed studies of CMOS digital circuit failures that will be carried out in the later chapters. Electrical properties of basic components such as field-effect transistors (FETs), resistors, capacitors, inductors, and interconnects in CMOS integrated circuits are reviewed, and characteristics of elementary circuits built by interconnecting these components, such as CMOS static and dynamic gates and linear and nonlinear amplifiers, are summarized. The study of circuit failure requires closed-form theoretical analyses of rather complex circuits. Therefore, two methods of closed-form analysis of CMOS circuits containing FETs and other passive components are discussed. These techniques of closed-form analysis become the basic tools in later chapters. The first method is to represent all active devices, components and interconnects by equivalent *linear* resistors and capacitors, whose values are determined from each component's physical model. Electrical properties of the equivalent resistance-capacitance circuit are analyzed using many useful analytical methods of conventional linear circuit theory (summarized in the later part of this chapter), and the results are translated back into the properties of digital CMOS circuits. In the second method, FETs are represented by gate voltage controlled *collapsible* current generators (devices that generate constant current if terminal voltages are not zero). As we study the second method of analysis in detail, we find that a digital circuit may be represented by an analog circuit, whose circuit configuration (connectivity of devices and components) changes with time. In this representation we recognize that information about how this change of circuit configuration takes place is more useful in understanding the circuit than the detailed numerical information or an algebraic formula of time-dependent voltages of the nodes. To make the best use of the information about the changes of the circuit configuration, we introduce the concept of circuit *states*, called *microstates*. Both of the methods (linear resistor model and the collapsible current generator model) are mathematically simple: Using one method or the other, most CMOS digital circuits can be analyzed in closed form.

To study CMOS digital circuits we require a good FET model, as well as a reasonable method of representing an integrated circuit by a lumped constant equivalent circuit. This chapter examines how to determine the best possible equivalent circuit and the approximations imposed by the equivalent circuits.

**1.2 Field-Effect Transistors**

MOSFET characteristics have been studied in great detail during thirty years of research. Sophisticated FET models are used in numerical simulation of MOS circuits. For application to studies of circuit failure, however, very high numerical precision is usually unnecessary. For research into circuit failure, simple device models that allow closed-form analysis are more desirable than better numerical accuracy attained by precise but complex models. This is because fundamental circuit characteristics are determined more from interconnection of devices than from the details of device characteristics. When the conclusions of theoretical circuit research are applied to practical IC design, the results obtained using the simple device model are calibrated using more accurate simulation results (this can be done by reinterpreting device model parameters). This two-step approach is more straightforward, more useful and often more accurate than *brute-force* circuit simulation.

Figure 1(a) shows a cross-section of N-channel MOSFET (NFET) in CMOS integrated circuit. The processing technology required to fabricate this structure is not discussed in detail. Interested readers are referred to standard references on IC processing [06]. The substrate of a conventional CMOS IC is N-type silicon, on the surface of which a P-type diffused area called a P-tub is formed. Thin oxide (gate oxide) of thickness *TOX* is grown on the P-tub surface, and polysilicon gate material is deposited on the top of the thin oxide layer. Polysilicon gate area (cross-hatched) is patterned using photolithography. Using the polysilicon gate features as mask, N+ drain and source impurities are implanted and diffused. Channel length *L* (often called *electrical* channel length) is approximately the same, but it is less than the gate polysilicon width (called *designed* channel length). Following further deposition of oxide insulation (intermediate oxide) source, gate, drain, and substrate are contacted by metallic (usually aluminum) conductors by cutting holes (windows) through the intermediate oxide. The finished NFETs have channel length *L,* width (often called FET size) *W,* and source-drain island width X, as defined in Fig. 1(a). The process of fabricating PFETs is interwoven with the NFET process. The only essential difference is that a PFET is fabricated on N-substrate (doped to make N-tub). An FET is a four-terminal device (Source, Drain, Gate, and Substrate). A PFET substrate terminal is common for all the PFETs on the same chip. We described the traditional N-substrate CMOS technology. Recently, P-type substrates are often used as starting material. In this case NFETs are fabricated on a globally connected P-tub, and PFETs are fabricated on isolated N-tubs. If the substrate is P-type, the NFET is a device having three independent terminals and a common substrate terminal, and a PFET has four independent terminals.

Suppose that the substrate and the source terminals are grounded, the gate is biased to positive voltage *VG,* and the drain to positive voltage *VD,* both relative to the grounded source. According to the theory by Weimer, the drain current *ID* of the NFET is given by [07]

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1a)

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (1b)

where *εOX* is the dielectric constant of silicon dioxide (0.345 × 10-12*F/cm)* and µ*N* is the mobility of electrons in the surface channel. *VTH* is called the threshold voltage. If *VTH* > 0 as in conventional *enhancement mode* CMOS FETs, a FET carries no drain current if the gate voltage is zero. Equations (1a) and (1b) are plotted in Fig. 1(b). Equations (1a) and (1b) are valid, subject to the following conditions:

1) The electric field parallel to the length of FET channel is low, so that the surface electron drift velocity is proportional to the local field within the channel, directed from drain to source (low-field condition).

2) The source/drain diffused island is shallow. The gate field (that induces channel charge) is approximately perpendicular to the channel, and the drain-source field (within the channel) is approximately parallel to the silicon surface. The channel is quite shallow (long-channel condition).

3) The substrate is lightly doped, so that the charge that exists between the conducting surface channel and the neutral bulk substrate is negligible.

In Eq. (1), the *BG* parameter that specifies FET current has special suffix *G,* which stands for the gradual channel, low-field FET model. For NFETs we use *BGN,* and for PFETs we use *BGP*.

Characteristics of PFETs have the same form as Eqs. (la) and (lb) except that *VD* is replaced by *Vs - VD* and *VG* by *VS - VG,* where *Vs* is the source voltage (the highest voltage relative to ground). In Eq. (1b), µ*P* becomes the mobility of the surface holes. Enhancement PFET threshold voltage *VTHN* is defined as a positive number. This choice of sign is convenient in writing the circuit equations. Equations (la) and (lb) give *idealized* FET characteristics. To explain characteristics of *real* MOSFETs in scaled-down CMOS ICs the assumptions used to derive Eqs. (1a) and (1b), and the parameters contained in them, must be qualified and reinterpreted. We must consider the effects of substrate doping, shape of the channel, identification of source and drain, and the high-field carrier transport effects.

**1.3 FET Threshold Voltage**

The simple FET characteristics of Eqs. (1a) and (1b) are derived assuming a lightly doped substrate. If the substrate is *doped* P-type [diffused P-tub shown in Fig. 1(a)], FET current-voltage characteristics deviate from Eqs. (1a) and (1b) because of the space-charge that exists between the channel and the doped substrate (or tub). The mechanism is as follows: Since (1) the surface channel is N-type (because it consists of thin surface layer heavily populated with electrons); (2) the substrate is P-type (that contains free holes); and (3) the electrons and the holes do not mix, there must be a layer depleted of holes immediately below the surface channel. Since the layer depleted of majority (positive) holes has negative *ionic* charge, the *depletion* layer carries negative charge. The surface conducting channel also carries negative electronic charge. The negative charge of the depletion layer must be induced in addition to the electron charge in the surface channel by the applied gate voltage. The most remarkable effects are positive shift (*increase*) in the threshold voltage *VTH* of a FET (increases if substrate doping is increased), and dependence of *VTH* on the substrate bias voltage (sourcesubstrate potential difference). This second effect is called the *back-bias effect.*

With reference to Fig. 2(a), NFET MN1 is fabricated on a grounded P-tub, and the source is biased to *VS* volts relative to the grounded P-tub (where *Vs >* 0). A small drain voltage relative to the source, *VDS* (where *VDS >* 0) is applied, and channel current *ID* is measured. As gate to source voltage, *VGS,* is increased from zero, *ID* begins to flow when *VGS* equals threshold voltage *VTH.* According to the theory of the back-bias effect, *VTH* is an increasing function of source voltage *VS,* and the dependence is written as

VTH = VTH(VS) (2)

Since the back-bias effect has significant impact on circuit design, we determine the function of Eq. (2) using simple physical reasoning. Let the threshold voltage of a *reference* NFET fabricated on a lightly doped substrate, but otherwise same as the first NFET, be *V**TH*0. Suppose that *V**TH*0 is given. Suppose that the substrate of the NFET under consideration is doped to *NA (acceptors/cm3).* Then the Fermi level of the P-type substrate is shifted down by [05]

φF= kT/q log (NA/n1)

from the center of the forbidden band, where *k* is Boltzmann's constant, *T* is the absolute temperature, *q* is the charge of an electron and *n1* is the intrinsic carrier density of silicon. We note that the Fermi level of the reference NFET substrate is at the center of the forbidden band. To create a conducting surface channel, the P-tub silicon surface must be converted to N-type *inverted* surface having comparable surface electron concentration (≈ *NA*). The potential of the silicon surface must be pulled up by 2φ*F*, and this potential must be supplied from the gate. Therefore a term (2φ*F*) must be added to *V**TH*0. As we see from this term, doping Ptub *increases* the NFET threshold voltage, or the NFET becomes *less* conductive. Intuitively an NFET fabricated on *more heavily doped* P-type substrate is *harder* to turn on. This explains the mechanism of positive shift of the threshold voltage, *VTH*, if substrate doping is increased.

Let us consider the effects of source-substrate voltage. When the substrate and the source are held at the same potential [inset in Fig. 2(a)], the negative space-charge layer beneath the conducting channel sustains potential 2φ*F*. Charge density per unit area of the space-charge layer is given by electrostatics as (P-tub is assumed uniformly doped)

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]. (3a)

If source to substrate voltage *VS (VS* > 0)is applied *Q*0, increases to *Q. Q* is found by replacing 2φ*F* in Eq. (3a) by 2φ*F* + *VS* as

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]. (3b)

and therefore the incremental charge in the space-charge layer, Δ*Q*, is given by

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]

Since this extra charge Δ*Q* must be induced by the positively biased gate, threshold voltage increases by

*ΔVHT = ΔQ/COX*

where *COX = εOX/TOX*> is the gate oxide capacitance per unit gate area. Therefore, the real threshold voltage is given by adding the two corrections to *V**TH*0(threshold voltage of the reference FET fabricated on lightly doped substrate) as

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]. (4a)

If dependence is separated out for convenience

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII] (4b)

where *VTH*(0) = *V**TH*0 + 2φ*F* and V0 = (2εSqNA · 2φF) 1/2/COX. Figure 2(b) shows function Δ*vTH*(*VS*/2φ*F*) defined in Eq. (4b) versus normalized source voltage VS/2φ*F*.

If we assume NA = 2 × 1016*acceptors/cm*3, the Fermi level at room temperature is

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]

below the center of the forbidden band, where thermal voltage *kT/q* = 25 *mV* and *ni* = 2 × 1010*cm*-3 at room temperature. We have

[MATHEMATICAL EXPRESSION NOT REPRODUCIBLE IN ASCII]

Therefore if *VS*/2φ*F* = 5, threshold voltage *VTH* increases by about 0.75 volt.

Substrate doping is the standard technique for FET threshold voltage control. Enhancement mode NFETs in digital CMOS ICs are now fabricated exclusively by doping P-tubs. If a lightly doped substrate is used, the threshold voltage of NFETs becomes negative, or NFETs conduct even at zero gate voltage (such NFETs are called *depletion* mode NFETs). There is immobile positive charge in the gate oxide immediately above the channel (conventionally called *QSS)* that induces a conducting surface channel in NFETs, even at zero gate voltage. We understand that enhancement mode NFETs in CMOS are inevitably associated with the back-bias effect.

The back-bias effect creates significant difficulties in setting the DC bias point of CMOS circuits that have series-connected FETs and that carry DC currents. Such a circuit structure is often seen if analog circuits are integrated into digital CMOS circuits. The differential amplifier shown in Fig. 3(a) is used to convert a small-amplitude differential signal into a single-ended CMOS level signal. Since this circuit is complex, full analysis will be given later (Section 2.11). Here we consider the most relevant points only. If both input FETs MN+ and MN– are to split current generated by MNO equally at the *balanced* operating point and are to operate as a linear differential amplifier at the bias point, the range of input voltage allowed is limited by the increased threshold voltage of NFET MN+ and MN- due to the back-bias effect. The range of input voltages allowed for linear operation is schematically shown in Fig. 3(b). If *V**IN*+ and *V**IN*-are reduced below the limit, common source voltage *VC* is reduced too much. A minimum *VC* voltage must be maintained at the common source node of the differential NFET pair to guarantee that the current generator, MNO, is well into the saturation region and the current is independent of *VC*. If this condition is not satisfied, the differential amplifier has poor CMRR (common mode rejection ratio-change of the two input voltages in the same polarity). The problem is aggravated if the power supply voltage is low.

*(Continues...)*

Excerpted fromTheory of CMOS Digital Circuits and Circuit FailuresbyMasakazu Shoji. Copyright © 1992 Princeton University Press. Excerpted by permission of PRINCETON UNIVERSITY PRESS.

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## Table of Contents

- FrontMatter, pg. i
- Contents, pg. v
- Preface and Acknowledgments, pg. xi
- List of Mathematical Symbols, pg. xvii
- Chapter 1. Physics of CMOS Integrated Circuits, pg. 3
- Chapter 2. Method of Analysis of CMOS Circuit Failures, pg. 88
- Chapter 3. Circuit Failures Due to Anomalous Signal Flow, pg. 176
- Chapter 4. Noise Phenomena in Digital Circuits, pg. 250
- Chapter 5. Circuit Failures Due to Timing Problems, pg. 337
- Chapter 6. Essential Uncertainty in CMOS Circuits, pg. 423
- Chapter 7. Design Failures of CMOS Systems, pg. 503
- Index, pg. 569