Pub. Date:
Springer Netherlands
Transistor Level Modeling for Analog/RF IC Design / Edition 1

Transistor Level Modeling for Analog/RF IC Design / Edition 1


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Product Details

ISBN-13: 9789048171484
Publisher: Springer Netherlands
Publication date: 11/19/2010
Edition description: Softcover reprint of hardcover 1st ed. 2006
Pages: 294
Product dimensions: 6.30(w) x 9.45(h) x 0.03(d)

About the Author

Dr. Grabinski, Dr. Nauwelaers and Dr. Scheurs organized the MOS-Modeling workshop at the European Solid-State Devices Conference (ESSDERC) in 2004, and due to popular request will do again at ESSDERC 2005 in Grenoble. Dr. Grabinski is in industry, at Freescale Semiconductor, while Dr. Nauwelaers and Dr. Schreurs are in academia.

Table of Contents

Foreword; H.Iwai
Introduction; W.Grabinski/ B.Nauwelaers/ D.Schreurs
1. 2/3D process and devices simulation; D.Donoval/ A.Vrbicky/ A.Chvala/P.Beno
2. PSP: An advanced surface-potential-based mosfet model; R.van Langevelde/ G.Gildenblat
3. EKV 3.0 mosfet model; M.Bucher/ A.Bazigos/ F.Drummenacher/ J-M.Sallese/ C.Enz
4. Modeling using high-frequency measurements; D.Schreurs
5. Empirical FET Models; I.Angelov
6. Modeling the SOI MOSFET Nonlinearities; B.Parvais/ A.Siligaris
7. Circuit level RF modeling and design; N.Itoh
8. On incorporating parasitic quantum effects in classical circuits simulations; F.Felgenhauer/ M.Begoin/ W.Mathis
9. Compact modeling of the MOSFET in VHDL-AMS; C.Lallement/ F.Pecheux/ A.Vachoux/ F.Pregaldiny
10. Compact modeling in Verilog-A; B.Troyanovsky/ P.O'Halloran/ M.Mierzwinski

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