Verilog Digital System Design

Verilog Digital System Design

by Zainalabedin Navabi

Other Format(BK&CD ROM)


Product Details

ISBN-13: 9780070471641
Publisher: McGraw-Hill Companies, The
Publication date: 07/27/1999
Series: McGraw-Hill Professional Engineering Series
Edition description: BK&CD ROM
Pages: 500
Product dimensions: 6.45(w) x 9.35(h) x 1.49(d)

About the Author

Zainalabedin Navabi (Boston, MA) is Professor of Electrical and Computer Engineering at Northeastern University. He is the author of Verilog Digital System Design.

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Chapter 1: Hardware Design Environments

As the size and complexity of digital systems increase, more computer-aided design tools are being introduced into the hardware design process. The early paper-and-pencil design methods have given way to sophisticated design entry, verification, and automatic hardware generation tools. The newest addition to this design methodology is the introduction of hardware description languages (HDLs). Although the concept of HDLs is not new, their widespread use in digital system design is no more than a decade old. Based on HDLs, new digital system computer-aided design (CAD) tools have been developed and are now being utilized by hardware designers. At the same time, researchers are finding more ways in which HDLs can improve the process of digital system design.

This chapter discusses the concept of hardware description languages and their use in a design environment. We will describe a design process, indicate where HDLs fit in this process, and describe simulation and synthesis, the two most frequent applications of HDLs.

1.1 Digital System Design Process

Figure 1.1 shows design steps that must be carried out in a typical design of a digital system. After the initial design idea, a designer goes through several design steps before a hardware implementation is obtained. At each step, the designer checks the result of the last transformation, adds more information to it, and passes it to the next design step.

Initially, a hardware designer starts with a design idea. A more complete definition of the intended hardware must then be developed from the initial design idea. Therefore, it is necessary for the designer to generatea behavioral definition of the system under design. The product of this design step may be a flowchart, a flow graph, or pseudocode. The designer specifies the overall functionality and an input-to-output mapping without giving architectural or hardware details of the system under design.

The next step in the design process is the design of the system data path. In this step, the designer specifies the registers and logic units necessary for implementation of the system. These components may be interconnected using either bidirectional or unidirectional busses. Based on the intended behavior of the system, the procedure for controlling the movement of data between registers and logic units through busses is then developed. Figure 1.2 shows a possible result of the data path design step. Data components in the data part of a circuit communicate via system busses, and the control procedure controls the flow of data between these components. As shown, this design step results in the architectural design of a system with specification of the control flow. No information about the implementation of the controller—hard-wired, encoding technique, or microprogrammed—is given in this step.

Logic design is the next step in the design process; it involves the use of primitive gates and flip-flops for the implementation of data registers, busses, logic units, and their controlling hardware. The result of this design step is a netlist of gates and flip-flops. Components used and their interconnections are specified in this netlist. Gate technology and even gate-level details of flip-flops are not included in this netlist.

The next design step is the transformation of the netlist of the previous level into a transistor list or layout. This involves the replacement of gates and flip-flops with their transistor equivalents or library cells. This step considers loading and timing requirements in its cell or transistor selection process. The final step in the design is manufacturing, which uses the transistor list or layout specification to burn fuses of a field-programmable device or to generate masks for IC fabrication.

1.1.1 Design automation

In the design process, much of the work of transforming a design from one form to another is tedious and repetitive. From the point of view of a digital system designer, a design is complete when an idea is transformed into an architecture or a data path description. The rest is routine work and involves tasks that a machine can do much faster than a talented engineer. The same can be said about the verification process; that is, a machine can be programmed to verify the functionality or timing of a designed circuit much more easily than any human can. Activities such as transforming one form of a design into another, verifying a design step output, or generating test data can be done at least in part by computers. This process is referred to as design automation (DA). Design automation tools can help the designer with design entry, hardware generation, test sequence generation, documentation, verification, and design management. Such tools perform their specific tasks on the output of each of the design steps of Fig. 1.1. For example, to verify the outcome of the data path design step, the bussing and register structure is fed into a simulation program. Also, to generate tests for register transfer faults, a design automation tool can be used for processing this level of system description and produce tests that can be used by test equipment. Other DA tools include a synthesizer that can automatically generate a netlist from the register and bus structure of the system under design, or one that generates an architectural layout based on the behavioral description of the system.

HDLs provide formats for representing the outputs of various design stages. An HDL-based DA tool for the analysis of a circuit uses this format for its input description, and a synthesis tool transforms its HDL input into an HDL which contains more hardware information. In the sections that follow, we discuss modeling, hardware description languages, digital system simulation, and hardware synthesis.

1.2 Hardware Modeling

A hardware designer models a circuit using available modeling tools. The level of abstraction for this modeling depends on the purpose for which the model is intended. If the model is to be used for documenting the functionality of the circuit, a very abstract behavioral-level model is necessary. On the other hand, if the model is to be used for verification of the timing of the circuit, a more detailed description is needed. A hardware engineer models his or her circuit so that it imitates the actual hardware component as closely and as accurately as possible for its intended purpose. A good modeler uses available hardware modeling tools to produce an elegant model of the hardware part.

Modeling tools available to a hardware engineer include paper and pencil, schematic capture programs, breadboarding facilities, and hardware description languages. The newest and most promising of these tools are hardware description languages. These modeling tools enable a hardware designer to model his or her circuit at many levels of abstraction for various design, analysis, and documentation purposes. Although all hardware description languages may be regarded as such, the level of model elegance and artistic representation of hardware may be different from one language to another...

Table of Contents

Chapter 1: Design Automation with Verilog

Chapter 2: Register Transfer Level Design with Verilog

Chapter 3: Verilog Language Concepts

Chapter 4: Combinational Circuit Description

Chapter 5: Sequential Circuit Description

Chapter 6: Component Test and Verification

Chapter 7: Detailed Modeling

Chapter 8: RT Level Design and Test
Appendix A: List of Keywords
Appendix B: Frequently Used Sysytem Tasks and Functions
Appendix C: Compiler Directives
Appendix D: Verilog Formal Syntax Definition
Appendix E: Verilog Assertion Monitors

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