Pub. Date:
Springer US
Wafer Level 3-D ICs Process Technology / Edition 1

Wafer Level 3-D ICs Process Technology / Edition 1

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Product Details

ISBN-13: 9781441945624
Publisher: Springer US
Publication date: 12/08/2010
Series: Integrated Circuits and Systems
Edition description: 2008
Pages: 410
Product dimensions: 6.10(w) x 9.25(h) x 0.36(d)

Table of Contents

Overview of Wafer-Level 3D ICs.- Monolithic 3D Integrated Circuits.- Stacked CMOS Technologies.- Wafer-Bonding Technologies and Strategies for 3D ICs.- Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies.- Cu Wafer Bonding for 3D IC Applications.- Cu/Sn Solid#x2013;Liquid Interdiffusion Bonding.- An SOI-Based 3D Circuit Integration Technology.- 3D Fabrication Options for High-Performance CMOS Technology.- 3D Integration Based upon Dielectric Adhesive Bonding.- Direct Hybrid Bonding.- 3D Memory.- Circuit Architectures for 3D Integration.- Thermal Challenges of 3D ICs.- Status and Outlook.

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