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Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration.
Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.
This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:
Latchup acts as a companion text to the author’s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology. Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration.
About the Author.
Chapter 1 CMOS Latchup.
1.1 CMOS Latchup.
1.2 Fundamental Concepts of Latchup Design Practice.
1.3 Building a CMOS Latchup Strategy.
1.4 CMOS Latchup Technology Migration Strategy.
1.5 Key Metrics of Latchup Design Practice.
1.6 CMOS Latchup Technology Trends and Scaling.
1.7 Key Developments.
1.8 Latchup Failure Mechanisms.
1.9 CMOS Latchup Events.
1.10 Electrostatic Discharge Sources.
1.11 Single Event Latchup.
1.12 Summary and Closing Comments.
Chapter 2 Bipolar Transistors.
2.1 The Bipolar Transistor and CMOS Latchup.
2.2 Bipolar Transistor.
2.3 Recombination Mechanisms.
2.4 Photon Currents in Metallurgical Junctions.
2.5 Avalanche Breakdown.
2.6 Vertical Bipolar Transistor Model.
2.7 Lateral Bipolar Transistor Models.
2.8 Lateral Bipolar Transistor Models with Electric Field Assist.
2.9 Lateral Bipolar Transistor Models–Nonuniform Vertical Profile.
2.10 Triple-Well Bipolar Transistor Models – Lateral and Vertical Contributions.
2.11 Merged Triple-Well Bipolar Models.
2.12 Summary and Closing Comments.
Chapter 3 Latchup Theory.
3.1 Regenerative Feedback.
3.1.1 Regenerative Feedback without Shunt Resistors and Alpha Representation.
3.2 Latchup Criterion with Emitter Resistance.
3.3 Holding Point Conditions.
3.4 Resistance Space.
3.5 Beta Space.
3.6 CMOS Latchup Differential Tetrode Condition.
3.7 CMOS Latchup Differential Holding Current Relationship.
3.8 CMOS Latchup Differential Holding Voltage Relationship.
3.9 CMOS Latchup Differential Resistance Relationship.
3.10 Differential Generalized Alpha Space Relationship.
3.11 High-Level Injection.
3.12 Transient Latchup.
3.13 External Latchup.
3.14 Alpha Particle Induced Latchup.
3.15 Summary and Closing Comments.
Chapter 4 Latchup Structures, Characterization and Test.
4.1 Guard Rings.
4.2 Latchup Characterization Structures – Single- and Dual-Well CMOS PNPN Test Structures.
4.3 Latchup Characterization – Basic Triple-Well pnpn Latchup Test Structures.
4.4 Latchup Characterization Techniques – pnpn Structures with Deep Trench.
4.5 Latchup Characterization and Testing – Nonautomated Test Systems and Methodology.
4.6 Latchup Characterization and Testing – Automatic Test Systems.
4.7 Latchup Characterization – Wafer-Level Test Procedures.
4.8 Latchup Characterization Techniques – Wafer-level Transmission Line Pulse Methodology.
4.9 Latchup Characterization – Transient Latchup.
4.10 Guard Ring Characterization.
4.11 Latchup Failure Analysis Techniques.
4.12 Summary and Closing Comments.
Chapter 5 CMOS Latchup Process Features and Solutions – Dual-Well and Triple-Well CMOS.
5.1 CMOS Semiconductor Process Solutions and CMOS Latchup.
5.5 pþ/nþ Scaling.
5.6 Isolation and Latchup.
5.8 Triple Well.
5.9 High-Dose Buried Layer.
5.10 Future Concepts.
5.11 Summary and Closing Comments.
Chapter 6 CMOS Latchup Process Features and Solutions – Bipolar and BiCMOS Technology.
6.1 CMOS Latchup in Bipolar and RF BiCMOS Technology.
6.2 Substrates – High-Resistance Substrates.
6.4 Alternative Isolation Concepts.
6.5 Trench Isolation (TI).
6.6 Deep Trench.
6.7 Triple-Well and BiCMOS Processes Integration.
6.8 Heavily Doped Buried Layer Implant and BiCMOS Technology.
6.9 Summary and Closing Comments.
Chapter 7 CMOS Latchup – Circuits.
7.1 Table of Circuit Interactions.
7.2 Intrabook Latchup Mechanisms.
7.3 Interbook Latchup Mechanisms.
7.4 Circuit Solutions – Input Circuit.
7.5 Power Supply Concepts.
7.6 Latchup Circuit Solutions – Power Supply to Power Supply Sequencing Circuitry.
7.7 Overshoot and Undershoot Clamp Networks.
7.8 Passive and Active Guard Rings.
7.9 Triple-Well Noise and Latchup Suppression Structures.
7.10 System-Level Issues.
7.11 Summary and Closing Comments.
Chapter 8 Latchup Computer Aided Design (CAD) Methods.
8.1 Latchup CAD Rules.
8.2 Design Rule Checking.
8.3 Computer-Aided Design Extraction Methodologies – Searching for the pnpn.
8.4 CAD Extraction Methods – Searching for the Guard Rings.
8.5 Latchup Extraction Methods and Tools.
8.6 Latchup CAD Simulation.
8.7 Summary and Closing Comments.
Posted February 20, 2011
Latchup is a very important topic for on-chip reliability of integrated systems. However, to the best of my knowledge, the previous book about this topic was published about 20 years ago. As the semiconductor technology evolves from micrometer range to nanometer range, every topic needs to be up-to-date, and latchup is no different in this regard. A book with full coverage on latchup and its implications in advanced technologies has been sought after for a while. This book by Dr. Voldman, a well-known IEEE fellow who has written a series of excellent books in ESD/latchup, serves this purpose perfectly. This book provides a very rigorous and comprehensive treatment. More importantly, this book also includes modern approaches and methodologies, especially on BiCMOS technology and on computer aided design (there is a full chapter dedicated to each of these topics).
Chapters 1 to 3 discuss latchup theories in scientific and rigorous approaches. Latchup is a special area in which simplistic rules of thumb are by no means adequate in nowadays' advanced design. The coverage of the theories is so comprehensive that many of the derivations can be directly used in one's on-chip design for latchup prevention. Starting from Chapter 4, there are lots of realistic examples of layout structures for latchup prevention, and schematics for characterization setup. These are very good guides and manuals from the authors' many years of experience in real design. Circuit examples are illustrated in the right places in the book. By Chapter 7, readers should have a deep understanding of the theories and layout guidelines. Then the readers are presented with circuit options and techniques. Chapter 8 on computer aided design techniques is a necessary discussion in modern IC design.
I highly recommend this book to engineers who need to deal with anything related to latchup, as well as students majoring in circuit or device design. Good understanding of this topic will be very helpful in one's career as a designer later on.
Posted May 24, 2009
This is yet another great book by the ESD expert Steven Voldman, IEEE Fellow. It is well-known that Dr. Voldman is an authoritative voice in circuit reliability. He writes with clarity, and with great wittiness, the state-of-the-art developments in circuit reliability. This comment is true for all of the books in his ESD series, but is particularly true for this latest book, Latchup. As a practicing engineer in ESD and reliability, I cannot recommend this book enough to all practicing professionals and students alike!Was this review helpful? Yes NoThank you for your feedback. Report this reviewThank you, this review has been flagged.
Posted April 18, 2008
Latchup is a well-known fundamental problem for CMOS technologies. Therefore, it is really a tough work to write a book about latchup. Base on the prior experiences in the semiconductor industry for over 25 years, Dr. Voldman has done a good demonstration to show how a well-known topic can be deeply discussed by a researcher. Not only the detail physics of latchup phenomenon, but also the recently hot topic of transient latchup (TLU) has been well discussed. Dr. Voldman also summarized the solutions (process, layout design, circuit design, CAD method, ¡K) to overcome the latchup issue for CMOS ICs. As a result, I¡¦d like to say : it is really a ¡§hao dongxi !!¡¨ (¡§good stuff¡¨ in Chinese).Was this review helpful? Yes NoThank you for your feedback. Report this reviewThank you, this review has been flagged.
Posted January 18, 2008
This book, Latchup, is by the same author (Steven Voldman) of a 3-book series on Electrostatic Discharge(ESD). There is renewed interest in CMOS latchup, and this book clearly explains the physics of this phenomenon. The author has many years of industry experience dealing with latchup reliability issues, and this experience shows in the expert manner in which he handles the topic. Voldman writes about physics of latchup in his unique style which is illuminating both for experts and beginners alike. I highly recommend this book series to all students of reliable integrated circuit design and latchup.Was this review helpful? Yes NoThank you for your feedback. Report this reviewThank you, this review has been flagged.