Title: Writing Testbenches: Functional Verification of HDL Models, Author: Janick Bergeron
Title: Writing Testbenches: Functional Verification of HDL Models, Author: Janick Bergeron
Title: Writing Testbenches using SystemVerilog, Author: Janick Bergeron
Title: Wireless Networks Information Processing and Systems: First International Multi Topic Conference, IMTIC 2008 Jamshoro, Pakistan, April 11-12, 2008 Revised Papers, Author: Dil Muhammad Akbar Hussain
Title: Windup in Control: Its Effects and Their Prevention, Author: Peter Hippe
Title: VLSI: Systems on a Chip: IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99) December 1-4, 1999, Lisboa, Portugal, Author: Luis Miguel Silveira
Title: VLSI Synthesis of DSP Kernels: Algorithmic and Architectural Transformations, Author: Mahesh Mehendale
Title: VLSI Design Methodologies for Digital Signal Processing Architectures, Author: Magdy A. Bayoumi
Title: VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design, Author: Ulrich Golze
Title: Virtual Components Design and Reuse, Author: Ralf Seepold
Title: VHDL for Simulation, Synthesis and Formal Proofs of Hardware, Author: Jean Mermet
Title: VHDL Coding Styles and Methodologies, Author: Ben Cohen
Title: VHDL Coding Styles and Methodologies, Author: Ben Cohen
Title: VHDL Answers to Frequently Asked Questions, Author: Ben Cohen
Title: VHDL Answers to Frequently Asked Questions, Author: Ben Cohen
Title: Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, Author: James M. Lee
Title: Verilog: Frequently Asked Questions: Language, Applications and Extensions, Author: Shivakumar  S. Chonnad
Title: Verilog HDL Synthesis: A Practical Primer, Author: J. Bhasker
Title: Verilog - 2001: A Guide to the New Features of the Verilog® Hardware Description Language, Author: Stuart Sutherland
Title: Vector Quantization and Signal Compression, Author: Allen Gersho

Pagination Links