A VHDL Synthesis Primer / Edition 2

A VHDL Synthesis Primer / Edition 2

by J. Bhasker
Pub. Date:
Star Galaxy Publishing

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A VHDL Synthesis Primer / Edition 2

Here is a practical and useful guide to VHDL synthesis. The purpose of this book is to explain the transformations that occur during the synthesis process from a VHDL model to a netlist. Constructs that are supported for synthesis are clearly explained with many examples with their synthesized netlists. The second edition is based on the IEEE standard NUMERIC_BIT/NUMERIC_STD arithmetic packages.

Product Details

ISBN-13: 9780965039192
Publisher: Star Galaxy Publishing
Publication date: 08/01/1998
Edition description: REVISED
Pages: 312
Product dimensions: 7.00(w) x 9.00(h) x (d)

Table of Contents

Chapter 1 Language Basics
1.2. Design Units
1.7. Simulating a Model

Chapter 2 Synthesis Basics
2.2. Synthesis in a Design Process
2.3. Value Holders for Hardware Modeling
2.4. Logic Value System
2.5. Computing Bit-widths
2.5.2. Type BIT_VECTOR
2.5.6. Signed and Unsigned Types

Chapter 3 Mapping Statements to Gates
3.4. Relational Operators
3.6. Process Statement
3.7. If Statement
3.8.1. Inferring Latches from Case Statements
3.9. Loop Statement
3.12.1. Multiple Clocks

Chapter 4 Model Optimizations
4.2. Conversion Functions
4.3. Type INTEGER
4.4. Common Subexpressions
4.5. Moving Code
4.10. Design Size
4.11. Using Parenthesis

Chapter 5 Verification
5.11. Initialization

Chapter 6 Modeling Hardware Elements for Synthesis
6.8. Latch with Asynchronous Preset and Clear
6.9. Modeling a Memory
6.10. Using a Pre-built Component
6.11. Writing Boolean Equations
6.12. Modeling a Finite State Machine
6.12.2. Mealy FSM
6.12.3. Encoding States

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