A VHDL Synthesis Primer / Edition 2

Overview

Here is a practical and useful guide to VHDL synthesis. The purpose of this book is to explain the transformations that occur during the synthesis process from a VHDL model to a netlist. Constructs that are supported for synthesis are clearly explained with many examples with their synthesized netlists. The second edition is based on the IEEE standard NUMERIC_BIT/NUMERIC_STD arithmetic packages.