Designing 2D and 3D Network-on-Chip Architectures

by Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch

Overview

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

Product Details

ISBN-13:	9781493945504
Publisher:	Springer New York
Publication date:	08/23/2016
Edition description:	Softcover reprint of the original 1st ed. 2014
Pages:	265
Product dimensions:	6.10(w) x 9.25(h) x 0.02(d)

Table of Contents

Part I: Network-on-Chip Design Methodology.- Network-on-Chip Technology: A Paradigm Shift.- NoC Modeling and Topology Exploration.- Communication Architecture.- Power and Thermal Effects and Management.- NoC-based System Integration.- NoC Verification and Testing.- The Spidergon STNoC.- Middleware Memory Management in NoC.- On Designing 3-D Platforms.- The SYSMANTIC NoC Design and Prototyping Framework.- Part II: Suggested Projects.- Projects on Network-on Chip.