Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
About the Author
Dr. Srinivasan Murali is a co-founder and CTO of iNoCs and a research scientist at the Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland. He received the MS and PhD degrees in Electrical Engineering from Stanford University in 2007. His research interests include interconnect design for Systems on Chips, with particular emphasis on developing CAD tools and design methods for Networks on Chips. His interests also include thermal modeling and reliability of multi-core systems. He has been actively involved in several conferences (such as DATE, CODES-ISSS, NoC symposium, VLSI-SoC) as a program committee member/session chair and is a reviewer for many leading conferences and journals. He is a recipient of the EDAA outstanding dissertation award for 2007 for his work on interconnect architecture design. He received a best paper award at the DATE 2005 conference and a best paper nomination at the ICCAD 2006 conference.
One of his papers has also been selected as one of "The Most Influential Papers of 10 Years DATE". He has over 30 publications in leading conferences and journals in this field.
Table of Contents
Preface. 1 Introduction. 1.1 Networks on Chips: Scalable interconnects for SoCs. 1.2 NoC Design Challenges. 1.3 Book Overview. 1.4 Related Work. Part I NoC Design Methods 2 Designing Crossbar Based Systems. 2.1 Problem Motivation and Application Traffic Analysis. 2.2 Design Methodology. 2.3 Exact Approach to Crossbar Synthesis. 2.4 Heuristic Approach to Crossbar Synthesis. 2.5 Experiments and Case Studies. 2.6 Summary. 3 Netchip Tool Flow For NoC Design. 3.1 Front-End Design Phase. 3.2 Architectural Design Phase: The xpipes NoC Library. 3.3 Summary. 4 Designing Standard Topologies. 4.1 On-Chip Traffic Modeling. 4.2 Problem Formulation. 4.3 Mapping and Physical Planning Algorithm. 4.4 Physical Planning. 4.5 Experiments and Case Studies. 4.6 Summary. 5 Designing Custom Topologies. 5.1 Objectives. 5.2 Input Models. 5.3 Design Algorithms. 5.4 Experiments and Case Studies. 5.5 Summary. 6 Supporting Multiple Applications. 6.1 The Aethereal NoC Architecture. 6.2 Design Methodology. 6.3 Use-Case Pre-Processing. 6.4 Unified Mapping-NoC Configuration. 6.5 Simulation Results. 6.6 Summary. 7 Supporting Dynamic Application Patterns. 7.1 NoC Design Challenges for CMPs. 7.2 Basics of the Synthesis Approach. 7.3 Design Flow. 7.4 Problem Formulation. 7.5 Synthesis Algorithm. 7.6 Experimental Results. 7.7 Summary. Part II NoC Reliability Mechanisms 8 Timing-Error Tolerant NoC Design. 8.1 The Double Sampling Technique. 8.2 Using Links as a Storage Medium. 8.3 T-error Link Designs. 8.4 Aggressive Switch/NI Design. 8.5 Dynamic Configuration of the NoC. 8.6 Experimental Results. 8.7 Summary. 9 Analysis of NoC Error Recovery Schemes. 9.1 Switch Architecture Design. 9.2 Energy Estimation and Models. 9.3 Experiments and Simulation Results. 9.4 Summary. 10 Fault-Tolerant Route Generation. 10.1 Multi-Path Routing with In-Order Delivery. 10.2 Path Selection Algorithm. 10.3 Multi-path Traffic Splitting. 10.4 Fault-Tolerance Support with Multi-path Routing. 10.5 Simulation Results. 10.6 Summary. 11 NoC Support for Reliable On-Chip Memories. 11.1 Analysis of Multimedia Software. 11.2 Baseline SoC Architecture and Extensions. 11.3 Run-time Fault Tolerant Schemes. 11.4 Experimental Results. 11.5 Summary. 12 Conclusions and Future Directions. 12.1 Putting it All Together. Bibliography.