Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
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Designing Reliable and Efficient Networks on Chips
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
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Designing Reliable and Efficient Networks on Chips
198
Designing Reliable and Efficient Networks on Chips
198Paperback(Softcover reprint of hardcover 1st ed. 2009)
$169.99
169.99
In Stock
Product Details
ISBN-13: | 9789048182008 |
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Publisher: | Springer Netherlands |
Publication date: | 11/05/2010 |
Series: | Lecture Notes in Electrical Engineering , #34 |
Edition description: | Softcover reprint of hardcover 1st ed. 2009 |
Pages: | 198 |
Product dimensions: | 6.10(w) x 9.25(h) x 0.02(d) |
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