ISBN-10:
079239058X
ISBN-13:
9780792390589
Pub. Date:
12/31/1989
Publisher:
Springer US
Hierarchical Modeling for VLSI Circuit Testing / Edition 1

Hierarchical Modeling for VLSI Circuit Testing / Edition 1

by Debashis Bhattacharya, John P. Hayes

Hardcover

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Product Details

ISBN-13: 9780792390589
Publisher: Springer US
Publication date: 12/31/1989
Series: The Springer International Series in Engineering and Computer Science , #89
Edition description: 1990
Pages: 160
Product dimensions: 6.10(w) x 9.25(h) x 0.02(d)

Table of Contents

1 Introduction.- 1.1 Background.- 1.2 Prior Work.- 1.2.1 Test Generation for Combinational Circuits.- 1.2.2 Test Generation for Sequential Circuits.- 1.2.3 High-level Test Generation.- 1.2.4 Fault Simulation.- 1.2.5 Design for Testability.- 1.3 Outline.- 2 Circuit and Fault Modeling.- 2.1 Vector Sequence Notation.- 2.2 Circuit and Fault Models.- 2.2.1 Circuit Model.- 2.2.2 Fault Model.- 2.3 Case Study: k-Regular Circuits.- 3 Hierarchical Test Generation.- 3.1 Vector Cubes.- 3.2 Test Generation.- 3.2.1 Repetitive Circuits.- 3.2.2 Pseudo-Sequential Circuits.- 3.2.3 High-Level Test Generation Algorithm.- 3.3 Implementation and Experimental Results.- 3.3.1 Circuit Description.- 3.3.2 Data Structures.- 3.3.3 Program Structure.- 3.3.4 Experimental Results.- 4 Design for Testability.- 4.1 Ad Hoc Techniques.- 4.1.1 Array-Like Circuits.- 4.1.2 Tree-Like Circuits.- 4.2 Level Separation (LS) Method.- 4.2.1 Functions Realizable by One-Dimensional ILA’s.- 4.2.2 Functions Realizable by Two-Dimensional ILA’s.- 4.3 Case Study: ALU.- 5 Concluding Remarks.- 5.1 Summary.- 5.2 Future Directions.- Appendix A: Proofs of Theorems.- A.1 Proof of Theorem 3.2.- A.2 Proof of Theorem 3.3.- A.3 Proof of Theorem 4.1.

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