High-Level System Modeling: Specification Languages

by Jean-Michel Bergé (Editor), Oz Levia (Editor), Jacques Rouillard (Editor)

Overview

A reactive system is one that is in continual interaction with its environment and executes at a pace determined by that environment. Examples of reactive systems are network prools, air-traffic control systems, industrial-process control systems etc. Reactive systems are ubiquitous and represent an important class of systems. Due to their complex nature, such systems are extremely difficult to specify and implement. Many reactive systems are employed in highly-critical applications, making it crucial that one considers issues such as reliability and safety while designing such systems. The design of reactive systems is considered to be problematic, and p.oses one of the greatest challenges in the field of system design and development. In this paper, we discuss specification-modeling methodologies for reactive systems. Specification modeling is an important stage in reactive system design where the designer specifies the desired properties of the reactive system in the form of a specification model. This specification model acts as the guidance and source for the implementation. To develop the specification model of complex systems in an organized manner, designers resort to specification modeling methodologies. In the context of reactive systems, we can call such methodologies reactive-system specification modeling methodologies.

Product Details

ISBN-13:	9781461359739
Publisher:	Springer US
Publication date:	09/27/2012
Series:	Current Issues in Electronic Modeling , #3
Edition description:	Softcover reprint of the original 1st ed. 1995
Pages:	162
Product dimensions:	6.30(w) x 9.45(h) x 0.02(d)

Table of Contents

Series presentation. Editors. Volume presentation. Contents. Contributors. 1. Specification-modeling methodologies for reactive-system design; A. Sarkar, et al. 2. Survey on languages for object oriented hardware design methodologies; G. Schumacher, W. Nebel. 3. VSPEC: a declarative requirements specification language for VHDL; P. Baraona, et al. 4. Communication prools implemented in hardware: VHDL generation from Estelle; J. Wytrebowicz, S. Budkowski. 5. An algorithm for the translation of SDL into synthesizable VHDL; R.J.O. Figuerido, I.S. Bonatti. 6. From LOTOS to VHDL; C.D. Kloos, et al. 7. Using an X-machine to model a video cassette recorder; M. Fairtlough, et al. Index.

Editorial Reviews

An update of the latest thought in hardware modeling for researchers, design engineers, and technical managers working in design automation and circuit design. Distinguishes between models that represent the desires and constraints of the designer and those that imitate something that already exists and can end in simulation or documentation. Also warns against leaning too far either towards over-specification, which can perpetrate constraints that were only meaningful in previous versions, or towards under-specification, which might lead to unnecessary work or even starting from scratch if the deferred details simply will not fit into the holes left for them. Annotation c. Book News, Inc., Portland, OR (booknews.com)

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