Legacy Data: A Structured Methodology for Device Migration in DSM Technology

Legacy Data: A Structured Methodology for Device Migration in DSM Technology

by Pallab Chatterjee

Paperback(Softcover reprint of the original 1st ed. 2003)

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Product Details

ISBN-13: 9781461349822
Publisher: Springer US
Publication date: 10/30/2012
Edition description: Softcover reprint of the original 1st ed. 2003
Pages: 132
Product dimensions: 6.10(w) x 9.25(h) x 0.01(d)

Table of Contents

Foreword. Acknowledgements. Glossary. 1. Introduction. 2. Legacy Data. 2.1. Modem SOC Flow. 2.2. Legacy Data Review. 3. Reasons for Data Migration. 3.1. Functional Reuse in Derivative Products. 4. New Rules for DSM Flows. 4.1. Device Geometries. 4.2. Wafer Type. 4.3. Isolation Technique. 4.4. Operating Voltage. 4.5. Process Design Rules. 4.6. Device Performance. 4.7. Interconnect Options. 4.8. Memory Techniques. 4.9. OPC Masking Techniques. 5. Structured Methodology. 5.1. Assumptions for Migration. 5.2. Flowchart of Methodology. 5.3. Sequence of the Methodology. 6. Screening Criteria for Blocks. 6.1. Introduction of Case Study. 6.2. Block Selection. 6.3. Description of Selection Criteria. 7. Process Compatibility. 7.1.Process Migration Tradeoffs. 7.2. Sample USB Block Tradeoff Analysis. 8. Test Bench Requirements. 8.1. Test Bench Minimum Requirements. 8.2. Digital Test Bench. 8.3. Device Level Test Bench. 8.4. USB Sample Summary. 9. Block Identification. 9.1. Physical and Design Views. 9.2. Multiple View Correction. 9.3. Hierarchy Tree. 9.4. Test Circuits, Clocks and Power Grids. 10. Design Retargeting. 10.1 Device Level ReDesign Stages. 10.2. Re-Engineering Process: Device Level Design. 10.3. Re-Engineering Process: Corner Based Design. 10.4. Summary for USB BlockMigration. 11. Design Validation. 11.1. Types of Validation. 11.2. Case Study Validation Summary. 12. Physical Design Migration. 12.1. Physical Migration Options. 13. Post Layout Validation. 13.1 Design Rule Checking: DRC. 13.2 Layout vs. Schematic: LVS. 13.3. Power Analysis: IR Drop. 13.4. Noise Analysis and Coupling: Signal Integrity. 13.5. RC Extraction for STA and for Device Stimulation. 13.6. Case Study Summary for Physical Verification. 14. Full Chip Verification. 14.1 Abstracts Required. Bibliography. Index.

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