Pub. Date:
Springer US
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits / Edition 1

Low-Power High-Level Synthesis for Nanoscale CMOS Circuits / Edition 1

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This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

Product Details

ISBN-13: 9781441945549
Publisher: Springer US
Publication date: 11/05/2010
Edition description: Softcover reprint of hardcover 1st ed. 2008
Pages: 302
Product dimensions: 6.10(w) x 9.25(h) x 0.36(d)

Table of Contents

Introduction.- High-Level Synthesis Fundamentals.- Power Modeling and Estimation at Transistor and Logic Gate Levels.- Architectural Power Modelling and Estimation.- Power Reduction Fundamentals.- Energy or Average Power Reduction.- Peak Power Reduction.- Transient Power Reduction.- Leakage Power Reduction.- Conclusions and Future Directions.

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