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Springer New York
Reliability of Nanoscale Circuits and Systems: Methodologies and Circuit Architectures / Edition 1

Reliability of Nanoscale Circuits and Systems: Methodologies and Circuit Architectures / Edition 1


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Product Details

ISBN-13: 9781441962164
Publisher: Springer New York
Publication date: 10/21/2010
Edition description: 2011
Pages: 195
Product dimensions: 6.30(w) x 9.20(h) x 0.80(d)

About the Author

Miloš Stanisavljevic received the M.S. degree in electrical engineering from the Faculty of Electrical Engineering, University of Belgrade, Belgrade, Serbia,
in 2004, and the Ph.D. degree in electrical engineering from the Swiss Federal
Institute of Technology (EPFL), Lausanne, Switzerland, in 2009. During
2004, he was an Analog Design and Layout Engineer for Elsys Design, Belgrade/
Texas Instruments, Nice. In the end of 2004, he joined Microelectronic
Systems Laboratory, EPFL, as a Research Assistant. During 2006, he was with International Business Machines Corporation (IBM) Research, Zurich,
for six months, where he was involved in the project related to reliability emulation in the state-of-the-art nanoscale CMOS technology. He is currently engaged in the field of reliability and fault-tolerant design of nanometer-scale systems. His current research interests include mixed-signal gate and system level design, reliability evaluation, and optimization. Dr. Stanisavljevic received a Scholarship for Students with Extraordinary Results Awarded by the Serbian Ministry of Education from 1996 to 2004.

Alexandre Schmid received the M.S. degree in Microengineering and the
Ph.D. degree in Electrical Engineering from the Swiss Federal Institute of
Technology (EPFL) in 1994 and 2000, respectively. He has been with the
EPFL since 1994, working at the Integrated Systems Laboratory as a research and teaching assistant, and at the Electronics Laboratories as a post-doctoral fellow. He joined the Microelectronic Systems Laboratory in 2002 as a Senior
Research Associate, where he has been conducting research in the fields of non-conventional signal processing hardware, nanoelectronic reliability, bioelectronic and brain-machine interfaces. Dr. Schmid has published over 70
peer-reviewed journal and conference papers. He has served in the conference committee of The International Conference on Nano-Networks since 2006, as technical program chair in 2008, and general chair in 2009. Dr. Schmid is an
Associate Editor of the IEICE ELEX. Dr. Schmid is also teaching at the Microengineering and Electrical Engineering Departments/Sections of EPFL.

Yusuf Leblebici received his B.Sc. and M.Sc. degrees in electrical engineering from Istanbul Technical University, in 1984 and in 1986, respectively, and his Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC) in 1990. Between 1991 and 2001,
he worked as a faculty member at UIUC, at Istanbul Technical University,
and at Worcester Polytechnic Institute (WPI). In 2000-2001, he also served as the Microelectronics Program Coordinator at Sabanci University.
Since 2002, Dr. Leblebici has been a Chair Professor at the Swiss Federal
Institute of Technology in Lausanne (EPFL), and director of Microelectronic
Systems Laboratory. His research interests include design of high-speed
CMOS digital and mixed-signal integrated circuits, computer-aided design of
VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis.

He is the coauthor of 4 textbooks, namely, Hot-Carrier Reliability of MOS
VLSI Circuits (Kluwer Academic Publishers, 1993), CMOS Digital Integrated
Circuits: Analysis and Design (McGraw Hill, 1st Edition 1996, 2nd Edition
1998, 3rd Edition 2002), CMOS Multichannel Single-Chip Receivers for
Multi-Gigabit Optical Data Communications (Springer, 2007) and Fundamentals of High Frequency CMOS Analog Integrated Circuits (Cambridge
University Press, 2009), as well as more than 200 articles published in various journals and conferences.

He has served as an Associate Editor of IEEE Transactions on Circuits and
Systems (II), and IEEE Transactions on Very Large Scale Integrated (VLSI)
Systems. He has also served as the general co-chair of the 2006 European
Solid-State Circuits Conference, and the 2006 European Solid State Device
Research Conference (ESSCIRC/ESSDERC). He is a Fellow of IEEE and has been elected as Distinguished Lecturer of the IEEE Circuits and Systems
Society for 2010-2011.

Table of Contents

1 Introduction 1

1.1 From Microelectronics to Nanoelectronics 1

1.2 Issues Related to Reliable Design 5

1.3 Outline of the Book 6

2 Reliability, Faults, and Fault Tolerance 7

2.1 Reliability and Fault Tolerance 7

2.2 Faults and Fault Models 10

2.3 Transistor Fault Model 13

3 Nanotechnology and Nanodevices 19

3.1 Single-Electron Transistors (SETs) 21

3.2 Resonant Tunneling Devices (RTDs) 23

3.3 Quantum Cellular Automata (QCA) 24

3.4 One-Dimensional (1D) Devices 25

3.5 CMOS-Molecular Electronics (CMOL) 27

3.6 Other Nanoelectronic Devices 28

3.7 Overview of Nanodevices' Characteristics 29

3.8 Challenges for Designing System Architectures Based on Nanoelectronic Devices 32

4 Fault-Tolerant Architectures and Approaches 35

4.1 Static Redundancy 36

4.1.1 Hardware Redundancy 36

4.1.2 Time Redundancy 41

4.1.3 Information Redundancy 41

4.1.4 Hybrid Approaches 42

4.1.5 Recent Techniques 43

4.2 Dynamic Redundancy 43

4.2.1 Reconfiguration 44

4.3 Overview of the Presented Fault-Tolerant Techniques 46

5 Reliability Evaluation Techniques 49

5.1 Historically Important Tools 51

5.2 Most Recent Progress in Reliability Evaluation 53

5.3 Monte Carlo Reliability Evaluation Tool 57

5.4 Summary 61

6 Averaging Design Implementations 63

6.1 The Averaging Technique 63

6.1.1 Feed-Forward ANN Boolean Function Synthesis Block 64

6.1.2 Four-Layer Reliable Architecture (4LRA) 66

6.1.3 Hardware Realizations of Averaging and Thresholding 68

6.1.4 Examples of Four-Layer Reliable Architecture Transfer Function Surfaces 70

6.2 Assessment of the Reliability of Gates and Small Blocks 76

6.2.1 Comparative Analysis of Obtained Results 77

6.3 Differential Signaling for Reliability Improvement 81

6.3.1 Fault-Tolerant Properties of Differential Signaling 81

6.3.2 Comparative Analysis of Obtained Results 82

6.4 Reliability of SET Systems 85

6.4.1 Reliability Evaluation 86

6.4.2 Comparison of Different Fault-Tolerant Techniques 89

6.5 Summary 92

7 Statistical Evaluation of Fault Tolerance Using Probability Density Functions 93

7.1 Statistical Method for the Analysis of Fault-Tolerant Techniques 94

7.2 Advanced Single-Pass Reliability Evaluation Method 103

7.2.1 Modified Single-Pass Reliability Evaluation Tool 104

7.2.2 Output PDF Modeling 112

7.3 Conclusions 118

8 Design Methodology: Reliability Evaluation and Optimization 121

8.1 Local-Level Reliability Evaluation 123

8.1.1 Dependency of Reliability on Logic Depth 125

8.1.2 Reliability Improvement by Logic Depth Reduction 127

8.1.3 Reliability Improvement of Different Fault-Tolerant Techniques 128

8.2 Optimal Reliability Partitioning 134

8.2.1 Partitioning to Small and Mid-Sized Partitions 136

8.2.2 Partitioning to Large-Sized Partitions 138

8.3 System-Level Evaluation and Optimization 139

8.3.1 R-Fold Modular Redundancy (RMR) 145

8.3.2 Cascaded R-Fold Modular Redundancy (CRMR) 151

8.3.3 Distributed R-Fold Modular Redundancy (DRMR) 155

8.3.4 NAND Multiplexing 161

8.3.5 Chip-Level Analysis 163

8.4 Conclusions 165

9 Summary and Conclusions 167

9.1 Reliability-Aware Design Methodology 167

9.2 Conclusions or Back into the Big Picture 169

A Probability of Chip and Signal Failure in System-Level Optimizations 171

A.1 Probability of Chip Failure for Cascaded R-Fold Modular Redundancy Architecture 171

A.1.1 Generalization 174

A.2 Probability of Input Signals Failure in Distributed R-Fold Modular Redundancy Architecture 175

References 177

Index 191

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