Scalable Shared Memory Multiprocessors / Edition 1

by Michel Dubois, Shreekant S. Thakkar

Overview

The workshop on Scalable Shared Memory Multiprocessors took place on May 26 and 27 1990 at the Stouffer Madison Hotel in Seattle, Washington as a prelude to the 1990 International Symposium on Computer Architecture. About 100 participants listened for two days to the presentations of 22 invited The motivation for this workshop was to speakers, from academia and industry. promote the free exchange of ideas among researchers working on shared-memory multiprocessor architectures. There was ample opportunity to argue with speakers, and certainly participants did not refrain a bit from doing so. Clearly, the problem of scalability in shared-memory multiprocessors is still a wide-open question. We were even unable to agree on a definition of "scalability". Authors had more than six months to prepare their manuscript, and therefore the papers included in this proceedings are refinements of the speakers' presentations, based on the criticisms received at the workshop. As a result, 17 authors contributed to these proceedings. We wish to thank them for their diligence and care. The contributions in these proceedings can be partitioned into four categories 1. Access Order and Synchronization 2. Performance 3. Cache Prools and Architectures 4. Distributed Shared Memory Particular topics on which new ideas and results are presented in these proceedings include: efficient schemes for combining networks, formal specification of shared­ memory models, correctness of trace-driven simulations,synchronization, various coherence prools, .

Product Details

ISBN-13:	9780792392194
Publisher:	Springer US
Publication date:	12/31/1991
Edition description:	1992
Pages:	329
Product dimensions:	6.10(w) x 9.25(h) x 0.03(d)

Table of Contents

Access Order and Synchronization.- 1. Combining Windows: The Key to Managing MIMD Combining Trees.- 2. Formal Specification of Memory Models.- 3. An Example of Correct Global Trace Generation.- 4. Locks, Directories, and Weak Coherence—a Recipe for Scalable Shared Memory Architectures.- Performance.- 5. What is Scalability?.- 6. Measuring Process Migration Effects Using an MP Simulator.- 7. Design and Analysis of a Scalable, Shared-memory System with Support for Burst Traffic.- 8. Scalable Cache Coherence Analysis for Shared Memory Multiprocessors.- 9. Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes.- Cache Prools and Architectures.- 10. Multiprocessor Consistency and Synchronization Through Transient Cache States.- 11. Delayed Consistency.- 12. The SCI Cache Coherence Prool.- 13. The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor.- Distributed Shared Memory.- 14. Scalability Issues of Shared Virtual Memory for Multicomputrers.- 15. Toward Large-Scale Shared Memory Multiprocessing.- 16. Local-area Memory in PLUS.- 17. A Dynamic Memory Management Scheme for Shared Memory Multiprocessors.

Editorial Reviews

A collection of edited papers that were first presented at a workshop held in May 1990 in conjunction with the International Symposium on Computer Architecture. They cover various fundamental aspects of scalable shared memory multiprocessors, such as how to build correct memory systems, how to predict their performance, and how to enhance the scalability through processor, interconnection, and cache designs. No index. Annotation c. Book News, Inc., Portland, OR (booknews.com)

Booknews