Separation Logic for High-level Synthesis

by Felix Winterstein

Overview

This book presents novel compiler techniques, which combine a rigorous mathematical framework, novel program analyses and digital hardware design to advance current high-level synthesis tools and extend their scope beyond the industrial ‘state of the art’. Implementing computation on customised digital hardware plays an increasingly important role in the quest for energy-efficient high-performance computing. Field-programmable gate arrays (FPGAs) gain efficiency by encoding the computing task into the chip’s physical circuitry and are gaining rapidly increasing importance in the processor market, especially after recent announcements of large-scale deployments in the data centre. This is driving, more than ever, the demand for higher design entry abstraction levels, such as the automatic circuit synthesis from high-level languages (high-level synthesis). The techniques in this book apply formal reasoning to high-level synthesis in the context of demonstrably practical applications.

Product Details

ISBN-13:	9783319532219
Publisher:	Springer International Publishing
Publication date:	02/28/2017
Series:	Springer Theses
Edition description:	1st ed. 2017
Pages:	132
Product dimensions:	6.10(w) x 9.25(h) x (d)

About the Author

Felix Winterstein received a Master's degree in electrical engineering and information technology from RWTH Aachen University, Germany, in 2009 and received the Ph.D. degree from the Imperial College London in 2016. He is currently a research associate in the Circuits and Systems Group at the same institution. His research area is digital hardware design with an emphasis on customised, reconfigurable computing using FPGAs. His interest focuses on the automatic circuit synthesis from high-level programming languages and advanced compiler techniques to extend the scope of existing design tools in this area.

Table of Contents

1. Introduction.- 2. High-level Synthesis of Dynamic Data Structures.- 3. Background.- 4. Heap Partitioning and Parallelisation.- 5. Custom Multi-Cache Architectures.- 6. Conclusion.- Bibliography.- Appendices.