The Interaction of Compilation Technology and Computer Architecture

by David J. Lilja (Editor), Peter L. Bird (Editor)

Overview

In brief summary, the following results were presented in this work: • A linear time approach was developed to find register requirements for any specified CS schedule or filled MRT. • An algorithm was developed for finding register requirements for any kernel that has a dependence graph that is acyclic and has no data reuse on machines with depth independent instruction templates. • We presented an efficient method of estimating register requirements as a function of pipeline depth. • We developed a technique for efficiently finding bounds on register requirements as a function of pipeline depth. • Presented experimental data to verify these new techniques. • discussed some interesting design points for register file size on a number of different architectures. REFERENCES [1] Robert P. Colwell, Robert P. Nix, John J O'Donnell, David B Papworth, and Paul K. Rodman. A VLIW Architecture for a Trace Scheduling Com­ piler. In Architectural Support for Programming Languages and Operating Systems, pages 180-192, 1982. [2] C. Eisenbeis, W. Jalby, and A. Lichnewsky. Compile-Time Optimization of Memory and Register Usage on the Cray-2. In Proceedings of the Second Workshop on Languages and Compilers, Urbana l/inois, August 1989. [3] C. Eisenbeis, William Jalby, and Alain Lichnewsky. Squeezing More CPU Performance Out of a Cray-2 by Vector Block Scheduling. In Proceedings of Supercomputing '88, pages 237-246, 1988. [4] Michael J. Flynn. Very High-Speed Computing Systems. Proceedings of the IEEE, 54:1901-1909, December 1966.

Product Details

ISBN-13:	9780792394518
Publisher:	Springer US
Publication date:	05/31/1994
Edition description:	1994
Pages:	285
Product dimensions:	6.10(w) x 9.25(h) x 0.36(d)

Table of Contents

1 Introduction and Overview.- 1 Introduction.- 2 Overview of the Book.- 3 Conclusion.- 2 Architectural Support for Compile-Time Speculation.- 1 Introduction.- 2 Speculative Execution.- 3 Global Instruction Scheduling.- 4 Experimental Results.- 5 Conclusion.- 3 Register Requirements for High Performance Code Scheduling.- 1 Buffer Space is Critical.- 2 Cyclic Scheduling.- 3 Register Requirements For Cyclic Schedules.- 4 Architectural Models.- 5 Bounding Register Requirements.- 6 Experiments.- 7 Summary.- 4 Data Dependencies in Decoupled, Pipelined Loops.- 1 Introduction.- 2 Architecture Overview.- 3 Background.- 4 Compiling Common Sub-Expressions.- 5 Loop Carried Dependencies.- 6 Conclusions.- 5 The Effects of Traditional Compiler Optimizations on Superscalar Architectural Design.- 1 Introduction and Background.- 2 Methods And Tools.- 3 Performance Metrics.- 4 Experimental Evidence.- 5 Conclusion.- 6 Dynamic Program Monitoring and Transformation Using the Omos Object Server.- 1 Introduction.- 2 OMOS and Linker Technology.- 3 Server Architecture.- 4 OMOS Program Monitoring.- 5 Reordering Strategies.- 6 Fragment Reordering.- 7 The Results.- 8 Related Work.- 9 Future Work.- 10 Conclusion.- 7 Performance Limits of Compiler-Directed Multiprocessor Cache Coherence Enforcement.- 1 Introduction.- 2 Coherence Schemes.- 3 Previous Work.- 4 Performance Comparisons.- 5 Conclusion.- 8 Compiling hpf for Distributed Memory Mimd Computers.- 1 Introduction.- 2 HPF Language.- 3 HPF Compiler.- 4 Partitioning.- 5 Communication.- 6 Run-time Support System.- 7 Optimizations.- 8 Experimental Results.- 9 Summary of Related Work.- 10 Summary and Conclusions.- 9 The Influence of the Object-Oriented Language Model on a Supporting Architecture.- 1 Introduction.- 2 Overview of the MUSHROOM architecture.- 3 Compilation technology.- 4 Software control of low-level features.- 5 Experiences designing the prototype.- 6 Summary and conclusions.- 10 Project Triton: Towards Improved Programmability of Parallel Computers.- 1 Introduction.- 2 Modula-2*.- 3 Optimization Techniques and Hardware Recommendations.- 4 Triton/1.- 5 Status and Future.- 6 Conclusion.

Editorial Reviews

Argues for integrating contemporary compilation technology with a supporting computer architecture to enhance the performance of overall systems, particularly parallel machines. Examines the interaction between the compiler and the architecture at the instruction level on uniprocessors, compilation issues for multiprocessor systems, and how features of the programming language can influence the design of both types of systems. Annotation c. Book News, Inc., Portland, OR (booknews.com)

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