Wide-Bandwidth High Dynamic Range D/A Converters

Wide-Bandwidth High Dynamic Range D/A Converters

Paperback(Softcover reprint of hardcover 1st ed. 2006)

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Product Details

ISBN-13: 9781441940261
Publisher: Springer US
Publication date: 11/29/2010
Series: The Springer International Series in Engineering and Computer Science , #871
Edition description: Softcover reprint of hardcover 1st ed. 2006
Pages: 202
Product dimensions: 6.30(w) x 9.45(h) x 0.02(d)

About the Author

Dr Konstantinos Doris is from Philips Research Laboratories in Eindhoven. His advisor, Prof. Arthur van Roermund, finds his work in the subject of high-speed DA converters an excellent candidate for us to publish.

Dr. Leenaerts is seen to be one of the top experts in RF Circuit Design in Europe.

Table of Contents

Glossary Abbreviations Preface
1: Digital to Analog conversion concepts
1.1 Functional aspects
1.2 Algorithmic aspects
1.3 Signal processing aspects
1.4 Circuit aspects
1.5 Conclusions
2: Framework for Analysis and Synthesis of DACs
2.1 Overview
2.2 Framework description

3: Current Steering DACs
3.1 Basic circuit
3.2 Implementations and technology impact

4: Dynamic limitations of Current Steering DACs
4.1 State of the art in dynamic linearity
4.2 Dynamic limitations of current steering DACs
4.3 Conclusions

5: Current Steering DAC circuit error analysis
5.1 Amplitude domain errors
5.2 Time domain errors
5.3 Conclusions

6: High-level modeling of Current Steering DACs
6.1 System modeling
6.2 Error properties and classification
6.3 Functional error generation mechanisms
6.4 Conclusions
7: Functional modeling of timing errors
7.1 Non-uniform timing
7.2 Stochastic non-uniform timing analysis
7.3 Deterministic non-uniform timing
7.4 Conclusions
8: Functional analysis of local timing errors
8.1 Local timing error analysis
8.2 High level architectural parameter tradeoffs: segmentation
8.3 Conclusions

9: Circuit analysis of local timing errors
9.1 Circuit analysis with linear models
9.2 Local timing error tradeoffs
9.3 Conclusions 10: Synthesis concepts for CS DACs
10.1 Information management in the CS DAC
10.2 Synthesis Policy
10.3 A-posteriori error correction methods
10.4 Conclusions
11: Design of a 12 bit 500 Msample/s DAC
11.1 Design approach
11.2 Architecture
11.3 Switched-Current cell
11.4 Decoder, data synchronization and conditioning
11.5 Layout
11.6 Experimental results
11.7 Conclusions
References
A: Output spectrum for timing errors
A.1 Power spectrum of y(t) for random timing errors
A.2 Spectrum of y(t) for deterministic timing errors

B: Literature data

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