Writing Testbenches: Functional Verification of HDL Models
CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Packages 231 VHDL Implementation 237 Packaging Bus-Functional Procedures 238 240 Creating a Test Harness 243 Abstracting the Client/Server Prool Managing Control Signals 246 Multiple Server Instances 247 Utility Packages 249 Autonomous Generation and Monitoring 250 Autonomous Stimulus 250 Random Stimulus 253 Injecting Errors 255 Autonomous Monitoring 255 258 Autonomous Error Detection Input and Output Paths 258 Programmable Testbenches 259 Configuration Files 260 Concurrent Simulations 261 Compile-Time Configuration 262 Verifying Configurable Designs 263 Configurable Testbenches 265 Top Level Generics and Parameters 266 Summary 268 CHAPTER 7 Simulation Management 269 Behavioral Models 269 Behavioral versus Synthesizable Models 270 Example of Behavioral Modeling 271 Characteristics of a Behavioral Model 273 x Writing Testbenches: Functional Verification of HDL Models Modeling Reset 276 Writing Good Behavioral Models 281 Behavioral Models Are Faster 285 The Cost of Behavioral Models 286 The Benefits of Behavioral Models 286 Demonstrating Equivalence 289 Pass or Fail? 289 Managing Simulations 292 294 Configuration Management Verilog Configuration Management 295 VHDL Configuration Management 301 SDF Back-Annotation 305 Output File Management 309 Regression 312 Running Regressions 313 Regression Management 314 Summary 316 APPENDIX A Coding Guidelines 317 Directory Structure 318 VHDL Specific 320 Verilog Specific 320 General Coding Guidelines 321 Comments 321 Layout 323 Syntax 326 Debugging 329 Naming Guidelines 329 Capitalization 330 Identifiers 332 Constants 334 334 HDL SpecificFilenames 336 HDL Coding Guidelines 336 337 Structure 337 Layout
1117011061
Writing Testbenches: Functional Verification of HDL Models
CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Packages 231 VHDL Implementation 237 Packaging Bus-Functional Procedures 238 240 Creating a Test Harness 243 Abstracting the Client/Server Prool Managing Control Signals 246 Multiple Server Instances 247 Utility Packages 249 Autonomous Generation and Monitoring 250 Autonomous Stimulus 250 Random Stimulus 253 Injecting Errors 255 Autonomous Monitoring 255 258 Autonomous Error Detection Input and Output Paths 258 Programmable Testbenches 259 Configuration Files 260 Concurrent Simulations 261 Compile-Time Configuration 262 Verifying Configurable Designs 263 Configurable Testbenches 265 Top Level Generics and Parameters 266 Summary 268 CHAPTER 7 Simulation Management 269 Behavioral Models 269 Behavioral versus Synthesizable Models 270 Example of Behavioral Modeling 271 Characteristics of a Behavioral Model 273 x Writing Testbenches: Functional Verification of HDL Models Modeling Reset 276 Writing Good Behavioral Models 281 Behavioral Models Are Faster 285 The Cost of Behavioral Models 286 The Benefits of Behavioral Models 286 Demonstrating Equivalence 289 Pass or Fail? 289 Managing Simulations 292 294 Configuration Management Verilog Configuration Management 295 VHDL Configuration Management 301 SDF Back-Annotation 305 Output File Management 309 Regression 312 Running Regressions 313 Regression Management 314 Summary 316 APPENDIX A Coding Guidelines 317 Directory Structure 318 VHDL Specific 320 Verilog Specific 320 General Coding Guidelines 321 Comments 321 Layout 323 Syntax 326 Debugging 329 Naming Guidelines 329 Capitalization 330 Identifiers 332 Constants 334 334 HDL SpecificFilenames 336 HDL Coding Guidelines 336 337 Structure 337 Layout
109.99 Out Of Stock
Writing Testbenches: Functional Verification of HDL Models

Writing Testbenches: Functional Verification of HDL Models

by Janick Bergeron
Writing Testbenches: Functional Verification of HDL Models

Writing Testbenches: Functional Verification of HDL Models

by Janick Bergeron

Overview

CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Packages 231 VHDL Implementation 237 Packaging Bus-Functional Procedures 238 240 Creating a Test Harness 243 Abstracting the Client/Server Prool Managing Control Signals 246 Multiple Server Instances 247 Utility Packages 249 Autonomous Generation and Monitoring 250 Autonomous Stimulus 250 Random Stimulus 253 Injecting Errors 255 Autonomous Monitoring 255 258 Autonomous Error Detection Input and Output Paths 258 Programmable Testbenches 259 Configuration Files 260 Concurrent Simulations 261 Compile-Time Configuration 262 Verifying Configurable Designs 263 Configurable Testbenches 265 Top Level Generics and Parameters 266 Summary 268 CHAPTER 7 Simulation Management 269 Behavioral Models 269 Behavioral versus Synthesizable Models 270 Example of Behavioral Modeling 271 Characteristics of a Behavioral Model 273 x Writing Testbenches: Functional Verification of HDL Models Modeling Reset 276 Writing Good Behavioral Models 281 Behavioral Models Are Faster 285 The Cost of Behavioral Models 286 The Benefits of Behavioral Models 286 Demonstrating Equivalence 289 Pass or Fail? 289 Managing Simulations 292 294 Configuration Management Verilog Configuration Management 295 VHDL Configuration Management 301 SDF Back-Annotation 305 Output File Management 309 Regression 312 Running Regressions 313 Regression Management 314 Summary 316 APPENDIX A Coding Guidelines 317 Directory Structure 318 VHDL Specific 320 Verilog Specific 320 General Coding Guidelines 321 Comments 321 Layout 323 Syntax 326 Debugging 329 Naming Guidelines 329 Capitalization 330 Identifiers 332 Constants 334 334 HDL SpecificFilenames 336 HDL Coding Guidelines 336 337 Structure 337 Layout

Product Details

ISBN-13: 9781475783445
Publisher: Springer US
Publication date: 04/14/2013
Edition description: Softcover reprint of the original 1st ed. 2002
Pages: 354
Product dimensions: 6.10(w) x 9.25(h) x 0.03(d)

About the Author


Janick Bergeron is the author of the Fatbrain.com bestseller Writing Testbenches: Functional Verification of HDL Models. He first worked on in-house simulation, synthesis, and static timing analysis tools at Nortel Networks in Ottawa, Canada. He was one of the architects of Nortel Networks' design verification process, which resulted in the first-time success of a completely new 10 GB ATM switch. Janick has been a methodology consultant for the past six years and has helped companies improve their verification processes, testbench implementations, and design quality. He has also helped verify various types of designs, including video CODECs, automated test equipment, and network components.

Table of Contents

What is Verification?.- Verification Tools.- The Verification Plan.- Behavioral Hardware Description Languages.- Stimulus and Response.- Architecting Testbenches.- Simulation Management.

What People are Saying About This

Chris Macinonski

In the latest edition, Mr. Bergeron continues to keep pace with the industry while providing world-class solutions to the verification problem...
—Senior Engineer, Qualis Design Corp.

Brian Bailey

Many companies out there now owe their current verification methodologies to this book. From it they have learned the secrets of efficiency, effectiveness and re-use as they apply to verification...
—Chief Technologist, Mentor Graphics Corp.

Ben Cohen

A must have bible for understanding verification issues and techniques with HDLs and HVLs, and for writing effective, readable and reusable testbenches within a best-in-class verification process.
—VhdlCohen Training

Grant Martin

Brilliant. Janick Bergeron has built on his ground-breaking first version of Writing Testbenches in this second edition...
—Fellow, Cadence Berkeley Labs

Foreword

Building on the first edition, " ...the most successful and popular contemporary verification textbook", the author raises the verification level of abstraction by introducing coverage-driven constrained random transaction-level self-checking testbenches - all made possible through the introduction of hardware verification languages (HVLs) such as e from Verisity and OpenVera from Synopsys...." Harry Foster, Chief Architect, Verplex Systems, Inc.
From the B&N Reads Blog
Page 1 of

Related Subjects

Computers
Science & Technology
Engineering
Computer Programming
Electrical & Electronic Engineering
Hardware Related Programming
Electronics - Circuits - Integrated
Hardware Related Programming - General & Miscellaneous
Electronics - Circuits - General
Computer hardware description languages
Electronic circuits
Computers
Science & Technology
Engineering
Computer Programming
Electrical & Electronic Engineering
Hardware Related Programming
Electronics - Circuits - Integrated
Hardware Related Programming - General & Miscellaneous
Electronics - Circuits - General
Computer hardware description languages
Electronic circuits

Customer Reviews