|Edition description:||Softcover reprint of the original 1st ed. 2002|
|Product dimensions:||6.10(w) x 9.25(h) x 0.03(d)|
About the Author
Janick Bergeron is the author of the Fatbrain.com bestseller Writing Testbenches: Functional Verification of HDL Models. He first worked on in-house simulation, synthesis, and static timing analysis tools at Nortel Networks in Ottawa, Canada. He was one of the architects of Nortel Networks' design verification process, which resulted in the first-time success of a completely new 10 GB ATM switch. Janick has been a methodology consultant for the past six years and has helped companies improve their verification processes, testbench implementations, and design quality. He has also helped verify various types of designs, including video CODECs, automated test equipment, and network components.
Table of ContentsForeword. Preface: Why This Book is Important. What This Book is About. What Prior Knowledge You Should Have. Reading Paths. VHDL vs Verilog. For More Information. 1: What is Verification? What is a Testbench. The Importance of Verification. Reconvergeance Model. The Human Factor. What Is Being Verified? Functional Verification Approaches. Testing vs. Verification. Verification and Design Reuse. The Cost of Verification. 2: Verification Tools. Linting Tools. Simulators. Third-Party Models. Waveform Viewers. Code Coverage. Verification Languages. Revision Control. Issue Tracking. Metrics. 3: The Verification Plan. The Role of the Verification Plan. Levels of Verification. Verification Strategies. From Specification to Features. From Features to Testcases. From Testcases to Testbenches. 4: Behavioral Hardware Description Languages. Behavioral vs. RTL Thinking. You Gotta Have Style! Structure of Behavioral Code. Data Abstractions. The HDL Parallel Engine. Verilog Portability Issues. 5: Stimulus and Response. Simple Stimulus. Verifying the Output. Self-Checking Testbenches. Complex Stimulus. Complex Response. Predicting the Output. 6: Architecting Testbenches. Reusable Verification Components. Verilog Implementation. VHDL Implementation. Autonomous Generation and Monitoring. Input and Output Paths. Verifying Configurable Designs. 7: Simulation Management. Behavioral Models. Pass or Fail? Managing Simulations. Regression. Appendix A: Coding Guidelines. Directory Structure. General Coding Guidelines. Naming Guidelines. HDL Coding Guidelines. Afterwords. Index.
What People are Saying About This
In the latest edition, Mr. Bergeron continues to keep pace with the industry while providing world-class solutions to the verification problem...
Senior Engineer, Qualis Design Corp.
Many companies out there now owe their current verification methodologies to this book. From it they have learned the secrets of efficiency, effectiveness and re-use as they apply to verification...
Chief Technologist, Mentor Graphics Corp.
A must have bible for understanding verification issues and techniques with HDLs and HVLs, and for writing effective, readable and reusable testbenches within a best-in-class verification process.
Brilliant. Janick Bergeron has built on his ground-breaking first version of Writing Testbenches in this second edition...
Fellow, Cadence Berkeley Labs