A High Performance Architecture for Prolog / Edition 1

by T.P. Dobry

Overview

Artificial Intelligence is entering the mainstream of com- puter applications and as techniques are developed and integrated into a wide variety of areas they are beginning to tax the pro- cessing power of conventional architectures. To meet this demand, specialized architectures providing support for the unique features of symbolic processing languages are emerging. The goal of the research presented here is to show that an archi- tecture specialized for Prolog can achieve a ten-fold improve- ment in performance over conventional, general-purpose architec- tures. This book presents such an architecture for high perfor- mance execution of Prolog programs. The architecture is based on the abstract machine descrip- tion introduced by David H.D. Warren known as the Warren Abstract Machine (W AM). The execution model of the W AM is described and extended to provide a complete Instruction Set Architecture (lSA) for Prolog known as the PLM. This ISA is then realized in a microarchitecture and finally in a hardware design. The work described here represents one of the first efforts to implement the W AM model in hardware. The approach taken is that of direct implementation of the high level WAM instruction set in hardware resulting in a elSe style archi- tecture.

Product Details

ISBN-13:	9780792390602
Publisher:	Springer US
Publication date:	01/31/1990
Series:	The Springer International Series in Engineering and Computer Science , #90
Edition description:	1990
Pages:	218
Product dimensions:	6.14(w) x 9.21(h) x 0.36(d)

Table of Contents

1 Introduction.- Logic Programming.- A Prolog Model.- Computer Architecture.- Other Symbolic Computing Processors.- Motivation.- Contributions.- Organization.- 2 An Abstract Prolog Machine.- Data Types.- Memory Areas.- Some Definitions.- Instruction Set.- Fundamental Operations.- Summary.- 3 A Modified WAM.- Address Space of the PLM.- Completing the Instruction Set.- Enhancements to the WAM.- Implementing Built-in Functions.- Summary.- 4 The Architecture Becomes a Machine.- The Prefetch Unit.- Defining a Basic Data Path.- Defining a Microengine.- Tuning the Data Path and the Microcode.- The Path to Memory.- Summary.- 5 The Experiment.- Methodology.- The Simulators.- The Benchmark Set.- Results.- Further Improvements to the PLM.- Summary.- 6 Conclusions.- Directions for Future Research.- Conclusions.