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Intel Xeon Phi Coprocessor High Performance Programming

Intel Xeon Phi Coprocessor High Performance Programming

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by James Jeffers, James Reinders

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Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, Intel Field Engineers, Application Engineers and Technical Consulting Engineers, to


Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, Intel Field Engineers, Application Engineers and Technical Consulting Engineers, to create this authoritative first book on the essentials of programming for this new architecture and these new products.

This book is useful even before you ever touch a system with an Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will generally increase your program performance on any system, and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture.

    • A practical guide to the essentials of the Intel Xeon Phi coprocessor
    • Presents best practices for portable, high-performance computing and a familiar and proven threaded, scalar-vector programming model
    • Includes simple but informative code examples that explain the unique aspects of this new highly parallel and high performance computational product
    • Covers wide vectors, many cores, many threads and high bandwidth cache/memory architecture

    Editorial Reviews

    From the Publisher
    "Reinders and Jeffers have written an outstanding book about much more than the Intel® Xeon Phi™. This is a comprehensive overview of the challenges in realizing the performance potential of advanced architectures, including modern multi-core processors and many-core coprocessors. The authors provide a cogent explanation of the reasons why applications often fall short of theoretical performance, and include steps that application developers can take to bridge the gap. This will be recommended reading for all of my staff." —James A. Ang, Ph.D. Senior Manager, Extreme-scale Computing, Sandia National Laboratories

    "The authors’ consummate knowledge of the architecture shines through in this excellent introduction to the fundamentals of programming for the Intel® Xeon Phi™ coprocessor."

    I highly recommend this engaging treatise to programmers interested in effectively utilizing the Intel® Xeon Phi™ coprocessor." —R. Glenn Brook, Ph.D., Chief Technology Officer, Joint Institute for Computational Sciences, Director, Application Acceleration Center of Excellence, University of Tennessee / Oak Ridge National Laboratory

    “The authors have provided a very readable, big-picture introduction to programming the Intel Xeon Phi Coprocessor. By chronicling step-by-step optimizations of several computational kernels, software interfaces are illustrated for getting the most out of key architectural features of the Intel Xeon Phi Coprocessor." —James L. Schwarzmeier, Cray Inc, January 2013.”

    "This book belongs on the bookshelf of every HPC professional. Not only does it successfully and accessibly teach us how to use and obtain high performance on the Intel MIC architecture, it is about much more than that. It takes us back to the universal fundamentals of high-performance computing including how to think and reason about the performance of algorithms mapped to modern architectures, and it puts into your hands powerful tools that will be useful for years to come." —Robert J. Harrison, Institute for Advanced Computational Science, Stony Brook University, from the Foreword

    Product Details

    Elsevier Science
    Publication date:
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    Barnes & Noble
    NOOK Book
    File size:
    7 MB

    Meet the Author

    Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel ® MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years.
    James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world’s first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James has published numerous articles, contributed to several books and is widely interviewed on parallelism. James has managed software development groups, customer service and consulting teams, business development and marketing teams. James is sought after to keynote on parallel programming, and is the author/co-author of three books currently in print including Structured Parallel Programming, published by Morgan Kaufmann in 2012.

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    Intel Xeon Phi Coprocessor High Performance Programming 5 out of 5 based on 0 ratings. 1 reviews.
    Are you a programmer? If you are, then this book is for you! Authors James Jeffers  and James Reinders, have done an outstanding job of writing a book that gives you the keys to general parallel programming. Authors Jeffers and Reinders, begin by Bringing together the essentials to high performance programming for an Intel Xeon Phi coprocessor. Next, they focus on accessing two of the three performance features of the many processing cores with floating point vector processing units and high-speed memory. Then, the authors examine the highly parallel programming with Intel Xeon Phi coprocessors, by using a more substantial yet still relatively simple code example that includes both computation and more complex memory access. They continue by giving an analogy to a real scientific code example that comes from the Riken Advanced Institute for computational Science in Japan. Next, the authors examine the rich set of options available for processors and Intel Xeon Phi coprocessors, with little specific Intel Xeon Phi knowledge required. Then, they show you why you need lots of task level parallelism; and, why you should first consider using OpenMP, Fortran 2008 DO CONCURRENT, Intel Threading Building Blocks, and Intel Cilk Plus. The authors continue by discussing offload models, which have a number of options that blur the distinction a little, specifically _Cilk_Shared; but, still manage distinct task/thread pools on each coprocessor and the host. Next, they examine key elements behind the design of the new Intel computing product line. Then, the authors look at software architecture and components that enable the coprocessor to operate seamlessly in a standard environment. They continue to focus more on knowledge useful to the administration of a system that contains Intel Xeon Phi coprocessors. Next, the authors show you how to use Intel MKL for the Intel Xeon Phi coprocessor. Then, they show you how the MPI programming model is a natural fit for clusters containing Intel Xeon Phi coprocessors. Finally, the authors include information on accurate timing, as it is related to the general topic of gaining insight into the behavior of applications. In this most excellent book, the authors worked to demystify the Intel Xeon Phi coprocessor and provide the foundational information that would fit in one book.  The authors also worked to explain common algorithms or patterns; and, how to implement them to utilize parallel programming.