Self-Checking and Fault-Tolerant Digital Design / Edition 1

Self-Checking and Fault-Tolerant Digital Design / Edition 1

by Parag K. Lala
ISBN-10:
0124343708
ISBN-13:
9780124343702
Pub. Date:
06/26/2000
Publisher:
Elsevier Science
ISBN-10:
0124343708
ISBN-13:
9780124343702
Pub. Date:
06/26/2000
Publisher:
Elsevier Science
Self-Checking and Fault-Tolerant Digital Design / Edition 1

Self-Checking and Fault-Tolerant Digital Design / Edition 1

by Parag K. Lala

Hardcover

$115.0 Current price is , Original price is $115.0. You
$115.00 
  • SHIP THIS ITEM
    Qualifies for Free Shipping
  • PICK UP IN STORE
    Check Availability at Nearby Stores
  • SHIP THIS ITEM

    Temporarily Out of Stock Online

    Please check back later for updated availability.


Overview

With VLSI chip transistors getting smaller and smaller, today's digital systems are more complex than ever before. This increased complexity leads to more cross-talk, noise, and other sources of transient errors during normal operation. Traditional off-line testing strategies cannot guarantee detection of these transient faults. And with critical applications relying on faster, more powerful chips, fault-tolerant, self-checking mechanisms must be built in to assure reliable operation.

Self-Checking and Fault-Tolerant Digital Design deals extensively with self-checking design techniques and is the only book that emphasizes major techniques for hardware fault tolerance. Graduate students in VLSI design courses as well as practicing designers will appreciate this balanced treatment of the concepts and theory underlying fault tolerance along with the practical techniques used to create fault-tolerant systems.


Product Details

ISBN-13: 9780124343702
Publisher: Elsevier Science
Publication date: 06/26/2000
Series: The Morgan Kaufmann Series in Computer Architecture and Design
Edition description: New Edition
Pages: 400
Product dimensions: 7.38(w) x 9.25(h) x (d)

About the Author

The author is currently a Professor in the Department of Electrical Engineering at North Carolina A&T State University. He is the author of more than 75 papers, and three books published by Prentice Hall. His research interests include design for testability, self-checking logic design, automatic logic synthesis of low power logic circuits, andCPLD/FPGA based system design. He received a M.S. from King's College, London, and a Ph.D. from the City University of London.

Table of Contents

Chapter 1 - Fundamentals of Reliability
Chapter 2 - Error Detecting and Correcting Codes
Chapter 3 - Self-Checking Combinational Logic Design
Chapter 4 - Self-Checking Checkers
Chapter 5 - Self-Checking Sequential Circuit Design
Chapter 6 - Fault-Tolerant Design
Appendix
Markov Models
From the B&N Reads Blog

Customer Reviews