Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits / Edition 1

Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits / Edition 1

ISBN-10:
0792395441
ISBN-13:
9780792395447
Pub. Date:
12/31/1994
Publisher:
Springer US
ISBN-10:
0792395441
ISBN-13:
9780792395447
Pub. Date:
12/31/1994
Publisher:
Springer US
Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits / Edition 1

Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits / Edition 1

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Overview

The goal of putting 'systems on a chip' has been a difficult challenge that is only recently being met. Since the world is 'analog', putting systems on a chip requires putting analog interfaces on the same chip as digital processing functions. Since some processing functions are accomplished more efficiently in analog circuitry, chips with a large amount of analog and digital circuitry are being designed. Whether a small amount of analog circuitry is combined with varying amounts of digital circuitry or the other way around, the problem encountered in marrying analog and digital circuitry are the same but with different scope. Some of the most prevalent problems are chip/package capacitive and inductive coupling, ringing on the RLC tuned circuits that form the chip/package power supply rails and off-chip drivers and receivers, coupling between circuits through the chip substrate bulk, and radiated emissions from the chip/package interconnects. To aggravate the problems of designers who have to deal with the complexity of mixed-signal coupling there is a lack of verification techniques to simulate the problem. In addition to considering RLC models for the various chip/package/board level parasitics, mixed-signal circuit designers must also model coupling through the common substrate when simulating ICs to obtain an accurate estimate of coupled noise in their designs. Unfortunately, accurate simulation of substrate coupling has only recently begun to receive attention, and techniques for the same are not widely known.
Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits addresses two major issues of the mixed-signal coupling problem — how to simulate it and how to overcome it. It identifies some of the problems that will be encountered, gives examples of actual hardware experiences, offers simulation techniques, and suggests possible solutions. Readers of this book should come away with a clear directive to simulate their design for interactions prior to building the design, versus a 'build it and see' mentality.


Product Details

ISBN-13: 9780792395447
Publisher: Springer US
Publication date: 12/31/1994
Series: The Springer International Series in Engineering and Computer Science , #302
Edition description: 1995
Pages: 280
Product dimensions: 6.10(w) x 9.25(h) x 0.03(d)

Table of Contents

1 Introduction.- 2 Sources of Noise and Methods of Coupling.- 2.1 Semiconductor Device Noise and Phenomena.- 2.2 Noise from Switching Voltage and Current.- 2.3 Inductive Coupling.- 2.4 Capacitive Coupling.- 2.5 Substrate Coupling.- 2.6 Summary.- 3 Semiconductor Device Simulation.- 3.1 Significance.- 3.2 Basic Equations.- 3.3 Boundary Conditions.- 3.4 Models of Physical Parameters.- 3.5 Spatial Discretization.- 3.6 Solution Methods.- 3.7 A Representative Example.- 3.8 Summary.- 4 Simplified Substrate Modeling and Rapid Simulation.- 4.1 Simplified Equation.- 4.2 Spatial Discretization.- 4.3 Boundary Conditions.- 4.4 Solution Methods.- 4.5 Asymptotic Waveform Evaluation (AWE).- 4.6 Substrate AWE Macromodels.- 4.7 Transient Simulation of AWE Macromodels.- 4.8 Substrate DC Macromodels.- 4.9 Matrix Solution.- 4.10 Results.- 4.11 Summary.- 5 Mesh Generation.- 5.1 Adaptive Mesh Refinement.- 5.2 A Priori Mesh Refinement.- 5.3 Summary.- 6 Substrate Modeling in Heavily-Doped Bulk Processes.- 6.1 Motivation.- 6.2 Single Node Substrate Model.- 6.3 Modified Single Node Substrate Model.- 6.4 Summary.- 7 Substrate Resistance Extraction for Large Circuits.- 7.1 Nested Macromodeling.- 7.2 Interpolated Macromodeling.- 7.3 Summary.- 8 Modeling Chip/Package Power Distribution.- 8.1 Effect of Power Bus Structure on Noise coupling.- 8.2 Summary.- 9 Controlling Substrate Coupling in Heavily-Doped Bulk Processes.- 9.1 Characterization of noise coupling concepts.- 9.2 P+ Bulk Wafer Characterization.- 9.3 Effect of Substrate contact placement on coupled noise.- 9.4 Effect of Package Inductance on Substrate noise.- 9.5 Noise Coupling Control Techniques.- 9.6 Summary.- 10 Controlling Substrate Coupling in Bulk P- Wafers.- 10.1 Bulk P- Wafer Characteristics.- 10.2 Substrate Attenuation Structures.-10.3 Summary.- 11 Chip/Package Shielding and Good Circuit Design Practice.- 11.1 Far Field Radiated Emissions.- 11.2 Effect of Chip Signal Isolation/Shielding Techniques on Noise.- 11.3 Effect of Packaging on Noise.- 11.4 Effect of Card Layout and Referencing on Noise.- 11.5 Effect of Circuit Topology on Noise.- 11.6 Summary.- 12 A Design Example.- 12.1 Design of a Mixed-Signal IC.- 12.2 Summary.- Appendices.- A Mesh Moments.- B Convergence Behaviour of Iterative Methods.
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