The Boundary-Scan Handbook

The Boundary-Scan Handbook

by Kenneth P. Parker

Paperback(Softcover reprint of the original 4th ed. 2016)

$169.99
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Product Details

ISBN-13: 9783319330693
Publisher: Springer International Publishing
Publication date: 08/23/2016
Edition description: Softcover reprint of the original 4th ed. 2016
Pages: 552
Product dimensions: 6.10(w) x 9.25(h) x (d)

About the Author

Dr. Kenneth P. Parker received his PHD at Stanford University. He has recently retired from a career with Hewlett-Packard and Agilent Technologies in the field of testing of electrical assemblies.

Table of Contents

List of Figuresxiii
List of Tablesxvi
List of Design-for-Test Rulesxvii
Preface to the First Editionxxi
Preface to the Second Editionxxiii
Preface to the Third Editionxxiv
Acknowledgementxxvii
1Boundary-Scan Basics and Vocabulary1
1.1Digital Test Before Boundary-Scan2
1.1.1Edge-Connector Functional Testing2
1.1.2In-Circuit Testing4
1.2The Philosophy of 1149.17
1.3Basic Architecture8
1.3.1The TAP Controller10
1.3.2The Instruction Register16
1.3.3Data Registers20
1.3.4The Boundary Register21
1.3.5Optimizing a Boundary Register Cell Design27
1.3.6Architecture Summary29
1.3.7Field-Programmable IC Devices30
1.3.8Boundary-Scan Chains31
1.4Non-Invasive Operational Modes33
1.4.1Bypass33
1.4.2Idcode33
1.4.3Usercode35
1.4.4Sample35
1.4.5Preload35
1.5Pin-Permission Operational Modes36
1.5.1Extest36
1.5.2Intest37
1.5.3Runbist38
1.5.4Highz39
1.5.5Clamp39
1.5.6Exceptions Due to Clocking40
1.6Extensibility40
1.7Subordination of IEEE 1149.141
1.8Costs and Benefits42
1.8.1Costs42
1.8.2Benefits44
1.8.3Trends46
1.9Other Testability Standards47
2Boundary-Scan Description Language (BSDL)49
2.1The Scope of BSDL52
2.1.1Testing52
2.1.2Compliance Assurance53
2.1.3Synthesis55
2.2Structure of BSDL57
2.3Entity Descriptions61
2.3.1Generic Parameter62
2.3.2Logical Port Description62
2.3.3Standard USE Statement63
2.3.4Use Statements64
2.3.5Component Conformance Statement64
2.3.6Device Package Pin Mappings65
2.3.7Grouped Port Identification66
2.3.8TAP Port Identification67
2.3.9Compliance Enable Description68
2.3.10Instruction Register Description68
2.3.11Optional Register Description70
2.3.12Register Access Description71
2.3.13Boundary-Scan Register Description72
2.3.14Runbist Execution Description75
2.3.15Intest Execution Description76
2.3.16User Extensions to BSDL77
2.3.17Design Warnings77
2.4Some advanced BSDL Topics78
2.4.1Merged Cells78
2.4.2Asymmetrical Drivers81
2.5BSDL Description of 74BCT837481
2.6Packages and Package Bodies84
2.6.1STD_1149_1_200185
2.6.2Cell Description Constants89
2.6.3Basic Cell Definitions BC_0 to BC_791
2.6.4Cells BC_8 to BC_10 Introduced in 200199
2.6.5User-Defined Boundary Cells101
2.6.6Definition of BSDL Extensions103
2.7Writing BSDL104
2.8Summary106
3Boundary-Scan Testing107
3.1Basic Boundary-Scan Testing108
3.1.1The 1149.1 Scanning Sequence108
3.1.2Basic Test Algorithm114
3.1.3The "Personal Tester" Versus ATE115
3.1.4In-Circuit Boundary-Scan117
3.1.5IC Test119
3.1.6IC BIST120
3.2Testing with Boundary-Scan Chains121
3.2.11149.1 Chain Integrity122
3.2.2Interconnect Test125
3.2.3Connection Tests138
3.2.4Interaction Tests140
3.2.5BIST and Custom Tests143
3.3Porting Boundary-Scan Tests144
3.4Boundary-Scan Test Coverage146
3.5Summary147
4Advanced Boundary-Scan Topics149
4.1DC Parametric IC Tests150
4.2Sample Mode Tests151
4.3Concurrent Monitoring154
4.4Non-Scan IC Testing155
4.5Non-Digital Device Testing158
4.6Mixed Digital/Analog Testing159
4.7Multi-Chip Module Testing161
4.8Firmware Development Support163
4.9In-System Configuration164
4.10Flash Programming166
4.11Hardware Fault Insertion167
4.12Power Pin Testing149
5Design for Boundary-Scan Test171
5.1Integrated Circuit Level DFT173
5.1.1TAP Pin Placement173
5.1.2Power and Ground Distribution174
5.1.3Instruction Capture Pattern178
5.1.4Damage Resistant Drivers179
5.1.5Output Pins180
5.1.6Bidirectional Pins182
5.1.7Post-Lobotomy Behavior182
5.1.8IDCODEs183
5.1.9User-Defined Instructions184
5.1.10Creation and Verification of BSDL184
5.2Board-Level DFT186
5.2.1Chain Configurations186
5.2.2TCK/TMS Distribution189
5.2.3Mixed Logic Families190
5.2.4Board Level Conflicts192
5.2.5Control of Critical Nodes193
5.2.6Power Distribution194
5.2.7Boundary-Scan Masters195
5.2.8Post-Lobotomy Board Behavior197
5.3System-Level DFT197
5.3.1The MultiDrop Problem198
5.3.2Coordination with Other Standards199
5.4Summary200
6Analog Measurement Basics201
6.1Analog In-Circuit Testing201
6.1.1Analog Failures202
6.1.2Measuring an Impedance204
6.1.3Errors and Corrections208
6.1.4Measurement Hardware210
6.2Limited Access Testing215
6.2.1Node Voltage Analysis216
6.2.2Testing With Node Voltages217
6.2.3Limited Access Node Voltage Testing219
6.3The Mixed-Signal Test Environment221
6.4Summary224
7IEEE 1149.4: Analog Boundary-Scan225
7.11149.4 Vocabulary and Basics226
7.1.1The Target Fault Spectrum227
7.1.2Extended Interconnect227
7.1.3Digital Pins229
7.1.4Analog Pins230
7.2General Architecture of an 1149.4 IC231
7.2.1Silicon "Switches"233
7.2.2The Analog Test Access Port (ATAP)234
7.2.3The Test Bus Interface Circuit (TBIC)235
7.2.4The Analog Boundary Module (ABM)240
7.2.5The Digital Boundary Module (DBM)246
7.3The 1149.4 Instruction Set247
7.3.1The EXTEST Instruction248
7.3.2The CLAMP Instruction251
7.3.3The HIGHZ Instruction251
7.3.4The PROBE Instruction251
7.3.5The RUNBIST Instruction252
7.3.6The INTEST Instruction252
7.4Other Provisions of 1149.4254
7.4.1Differential ATAP Port254
7.4.2Differential I/O255
7.4.3Partitioned Internal Test Buses257
7.4.4Specifications and Limits260
7.5Design for 1149.4 Testability261
7.5.1Integrated Circuit Level261
7.5.2Board Level263
7.5.3System Level264
7.6Summary265
8IEEE 1149.6: Testing Advanced I/O267
8.1The Advanced I/O Problem268
8.1.1Traditional Inter-IC Communication268
8.1.2Advanced Inter-IC Communication270
8.1.3AC Coupled Signal Paths275
8.1.4Testing Advanced I/O277
8.21149.6 Vocabulary and Basics279
8.2.1Advanced I/O279
8.2.2Signal Pin Categories279
8.2.3Operational Modes280
8.3Test Facilities for AC Pins281
8.3.1Provisions for All Signal Pins281
8.3.2Provisions for AC Pin Drivers281
8.3.3AC/DC Selection Cells284
8.3.4Provisions for AC Pin Receivers286
8.4The Defect Model for 1149.6287
8.5The 1149.6 Test Receiver290
8.5.1Test Receiver Definitions290
8.5.2Transitions291
8.5.3Test Receiver DC Response293
8.5.4Test Receiver AC Response296
8.5.5Guaranteed AC-Coupling299
8.5.6An Integrated AC/DC Test Receiver299
8.5.7Initializing and Capturing Hysteretic Memory300
8.6BSDL Extensions for 1149.6302
8.6.1Boundary Registers Cells for 1149.6303
8.6.2STD_1149_6_2003308
8.6.3Example 1149.6 Device and BSDL310
8.7Design for 1149.6 Testability316
8.7.1Integrated Circuit Level DFT316
8.7.2Board-Level DFT317
8.8Summary318
9IEEE 1532: In-System Configuration319
9.1IEEE 1532 Vocabulary and Basics321
9.1.1Fixed System Pins321
9.1.2ISC System Pins322
9.1.3System Modal States322
9.1.4System I/O Behavior328
9.1.5ISC Pin I/O Cell Design329
9.2Programming Features of IEEE 1532333
9.2.1Core 1532 Programming Instructions334
9.2.2Programming a Single, Simple 1532 Device336
9.2.3Concurrent Programming of Multiple Devices339
9.3Design for IEEE 1532 Programmability339
9.4Epilog: What Next for 1149.1, 1149.4, 1149.6 and 1532?341
A.BSDL Syntax Specifications345
A.1Conventions345
A.2Lexical elements of BSDL346
A.3Notes on syntax definition349
A.4BSDL Syntax351
A.5User Package Syntax355
A.61149.6 Extention Attribute Syntax355
Bibliography357
Index365

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