VLSI Design and Test: 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers

by Ambika Prasad Shah (Editor), Sudeb Dasgupta (Editor), Anand Darji (Editor), Jaynarayan Tudu (Editor)

Overview

This book constitutes the proceedings of the 26th International Symposium on VLSI Design and Test, VDAT 2022, which took place in Jammu, India, in July 2022.
The 32 regular papers and 16 short papers presented in this volume were carefully reviewed and selected from 220 submissions. They were organized in topical sections as follows: Devices and Technology; Sensors; Analog/Mixed Signal; Digital Design; Emerging Technologies and Memory; System Design.

Product Details

ISBN-13:	9783031215148
Publisher:	Springer-Verlag New York, LLC
Publication date:	12/16/2022
Series:	Communications in Computer and Information Science , #1687
Sold by:	Barnes & Noble
Format:	eBook
File size:	130 MB
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Table of Contents

​Devices and Technology.- FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source &Drain of 5nm Nanosheet.- Differential Multi-bit Through Glass Vias for Three-Dimensional Integrated Circuits.- Design Of A Low-Voltage Charge-Sensitive Preamplifier Interfaced with Piezoelectric Tactile Sensor For Tumour Detection.- Design, Simulation and Optimization of Aluminum Nitride Based Accelerometer.- Low Loss Enabled Semi-Superjunction 4H-SiC IGBT for High Voltage and Current Application.- Implications of Field Plate HEMT towards Power Performance at Microwave X – Band.- Investigation of Traps in AlGaN/GaN HEMT Epitaxial Structure Using Conductance Method.- Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective.- Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α).- i-MAX: Just-In-Time Wakeup of Maximally Gated Router for Power Efficient Multiple NoC.- Quantum Tunnelling and Themonic Emission,Transistor simulation.- Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor.- Sensors.- Fabrication, Optimization and Testing of Photoconductively Tuned SAW Device using CBD Method.- High Resolution Temperature Sensor Signal Processing ASIC for Cryo Cooler Electronics.- Analog/Mixed Signal.- Low Power, Wideband SiGe HBT LNA Covering 57-64 GHz Band.- Four Differential Channels, Programmable Gain, Programmable Data Rate Delta Sigma ADC.- Low Power Dual-Band Current Reuse-based LC-Voltage Controlled Oscillator with Shared Inductor for IoT Applications.- Aging Resilient and Energy Efficient Ring Oscillator for PUF design.- A GaN based Reverse Recovery Time Limiter Circuit Integrated with A Low Noise Amplifier.- Novel configuration of multi-mode universal shadow filter employing a newactive block.- Highly Non-linear Feed-Forward Arbiter PUF against Machine Learning Attacks.- An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible Circuits.- An Approach towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array.- Digital Design.- MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANN.- Metastable SR Flip-Flop based True Random Number Generator using QCA Technology.- Hardware Design of Two Stage Reference Free Adaptive Filter for ECG Denoising.- A Reconfigurable Arbiter PUF based on VGSOT MTJ.- Pass Transistor XOR Gate based Radiation Hardened RO-PUF.- QCA Technology based 8-bit TRNG Design for Cryptography Applications.- Signal Integrity and Power Loss Analysis for different Bump Structures in Cylindrical TSV.- Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect.- Low Cost Hardware Design of ECCScalar Multiplication.- Scalable Construction of Formal Error Guaranteed LUT-based Approximate Multipliers with Analytical Worst-Case Error Bound.- Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity against Process Variations.- High Performance Ternary Full Adder in CNFET-Memristor Technology.- Synthesis of LUT based Approximating Adder Circuits with Formal Error Guarantees.- Emerging Technologies and Memory.- CAR: Community Aware Graph Reordering for Efficient Cache Utilization in Graph Analytics.- Indigenous Fab-Lab Hybrid Device Integration for Phase Change Memory for In-Memory Computing.- Resistive switching behavior of TiO2/(PVP:MoS2) nanocomposite bilayer hybrid RRAM.- RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone Environments.- Disrupting Low-write-energy vs. Fast-read Dilemma in RRAM to Enable L1 Instruction Cache.- System Design.- Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture.- Development of Distributed Controller for Electronic Beam Steering using Indigenous Rad-Hard ASIC.- Tile Serial Protocol (TSP) ASIC for Distributed Controllers of Space-borne Radar.- A deep dive into CORDIC Architectures to implement trigonometric functions.- Impact of Operand Ordering in Approximate Multiplication in Neural Network and Image Processing Applications.- An Overlap-and-Add based Time-domain Acceleration of CNNs on FPGA-CPU Systems.- Low Cost Implementation of Deep Neural Network On Hardware.