SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

by Chris Spear, Greg Tumbush

Overview

Based on the bestselling first edition this extensively revised second edition includes the relevant changes that apply to the 2008 version of the SystemVerilog Language Reference Manual (LRM). Significant changes include: The revision of nearly every paragraph and example, The addition of 70 new examples including larger ones such as a directed testbench at the end of chapter four and a complete constrained random testbench in the new chapter eleven, The improvement of the index with 50% more entries and cross references, The inclusion of new chapters: "A Complete SystemVerilog Testbench" and "Interfacing with C".

About the Author:
Chris Spear is a Verification Consultant for Synopsys and has advised companies around the world on testbench methodology

Product Details

ISBN-13:	9781461407157
Publisher:	Springer-Verlag New York, LLC
Publication date:	02/14/2012
Sold by:	Barnes & Noble
Format:	eBook
File size:	16 MB
Note:	This product may take a few minutes to download.

About the Author

Chris Spear has been working in the ASIC design and verification field for 30 years. He started his career with Digital Equipment Corporation (DEC) as a / CAD Engineer on DECsim, connecting the first Zycad box ever sold, and then a hardware Verification engineer for the VAX 8600, and a hardware behavioral simulation accelerator. He then moved on to Cadence where he was an Application Engineer for Verilog-XL, followed by a stint at Viewlogic. Chris is currently employed at Synopsys Inc. as a Verification Consultant, a title he created a dozen years ago. He has authored the first and second editions of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features. Chris earned a BSEE from Cornell University in 1981. In his spare time, Chris enjoys road biking in the mountains and traveling with his wife.

Greg Tumbush has been designing and verifying ASICs and FPGAs for 13 years. After working as a researcher in the Air Force Research Labs (AFRL) he moved to beautiful Colorado to work with Astek Corp as a Lead ASIC Design Engineer. He then began a 6 year career with Starkey Labs, AMI Semiconductor, and ON Semiconductor where he was an early adopter of SystemC and SystemVerilog. In 2008, Greg left ON Semiconductor to form Tumbush Enterprises, LLC where he has been consulting clients in the areas of design, verification, and backend to ensure first pass success. He is also a part time Instructor at the University of Colorado, Colorado Springs where he teaches senior and graduate level digital design and verification courses. He has numerous publications which can be viewed at www.tumbush.com. Greg earned a Ph.D. from the University of Cincinnati in 1998.

Table of Contents

List of Examples     xiii
List of Figures     xxv
List of Tables     xxvii
Preface     xxix
Acknowledgments     xxxv
Verification Guidelines     1
The Verification Process     2
The Verification Methodology Manual     4
Basic Testbench Functionality     5
Directed Testing     5
Methodology Basics     7
Constrained-Random Stimulus     8
What Should You Randomize?     10
Functional Coverage     13
Testbench Components     14
Layered Testbench     15
Building a Layered Testbench     21
Simulation Environment Phases     22
Maximum Code Reuse     23
Testbench Performance     23
Conclusion     24
Data Types     25
Built-In Data Types     25
Fixed-Size Arrays     28
Dynamic Arrays     34
Queues     36
Associative Arrays     38
Linked Lists     40
Array Methods     41
Choosing a Storage Type     46
Creating New Types with typedef     48
Creating User-Defined Structures     50
Type conversion     52
Enumerated Types     55
Constants     59
Strings     59
Expression Width     60
Conclusion     61
Procedural Statements and Routines     63
Procedural Statements     63
Tasks, Functions, and Void Functions     65
Task and Function Overview     65
Routine Arguments     66
Returning from a Routine     72
Local Data Storage     73
Time Values     75
Conclusion     77
Connecting the Testbench and Design     79
Separating the Testbench and Design     80
The Interface Construct     82
Stimulus Timing     88
Interface Driving and Sampling     96
Connecting It All Together     103
Top-Level Scope     104
Program - Module Interactions     106
System Verilog Assertions     107
The Four-Port ATM Router     109
The ref Port Direction     117
The End of Simulation     118
Directed Test for the LC3 Fetch Block     118
Conclusion      124
Basic OOP     125
Introduction     125
Think of Nouns, not Verbs     126
Your First Class     126
Where to Define a Class     127
OOP Terminology     128
Creating New Objects     129
Object Deallocation     132
Using Objects     134
Static Variables vs. Global Variables     134
Class Methods     138
Defining Methods Outside of the Class     139
Scoping Rules     141
Using One Class Inside Another     144
Understanding Dynamic Objects     147
Copying Objects     151
Public vs. Local     157
Straying Off Course     157
Building a Testbench     158
Conclusion     159
Randomization     161
Introduction     161
What to Randomize     162
Randomization in SystemVerilog     165
Constraint Details     167
Solution Probabilities     178
Controlling Multiple Constraint Blocks     182
Valid Constraints     183
In-line Constraints     184
The pre_randomize and post_randomize Functions      185
Random Number Functions     187
Constraints Tips and Techniques     187
Common Randomization Problems     193
Iterative and Array Constraints     195
Atomic Stimulus Generation vs. Scenario Generation     204
Random Control     207
Random Number Generators     209
Random Device Configuration     213
Conclusion     216
Threads and Interprocess Communication     217
Working with Threads     218
Disabling Threads     228
Interprocess Communication     232
Events     233
Semaphores     238
Mailboxes     240
Building a Testbench with Threads and IPC     253
Conclusion     257
Advanced OOP and Testbench Guidelines     259
Introduction to Inheritance     260
Blueprint Pattern     265
Downcasting and Virtual Methods     270
Composition, Inheritance, and Alternatives     274
Copying an Object     279
Abstract Classes and Pure Virtual Methods     282
Callbacks     284
Parameterized Classes     290
Conclusion      293
Functional Coverage     295
Coverage Types     298
Functional Coverage Strategies     301
Simple Functional Coverage Example     303
Anatomy of a Cover Group     305
Triggering a Cover Group     307
Data Sampling     310
Cross Coverage     319
Generic Cover Groups     325
Coverage Options     327
Analyzing Coverage Data     329
Measuring Coverage Statistics During Simulation     331
Conclusion     332
Advanced Interfaces     333
Virtual Interfaces with the ATM Router     334
Connecting to Multiple Design Configurations     342
Procedural Code in an Interface     347
Conclusion     350
A Complete Systemverilog Testbench     351
Design Blocks     351
Testbench Blocks     356
Alternate Tests     377
Conclusion     379
Interfacing With C     381
Passing Simple Values     382
Connecting to a Simple C Routine     385
Connecting to C++     393
Simple Array Sharing     398
Open arrays     400
Sharing Composite Types     404
Pure and Context Imported Methods     407
Communicating from C to SystemVerilog     407
Connecting Other Languages     418
Conclusion     419
References     421
Index     423