ISBN-10:
1461407141
ISBN-13:
9781461407140
Pub. Date:
02/14/2012
Publisher:
Springer US
SystemVerilog for Verification: A Guide to Learning the Testbench Language Features / Edition 3

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features / Edition 3

by Chris Spear, Greg Tumbush
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Product Details

ISBN-13: 9781461407140
Publisher: Springer US
Publication date: 02/14/2012
Edition description: 3rd ed. 2012
Pages: 464
Sales rank: 955,053
Product dimensions: 6.30(w) x 9.30(h) x 1.30(d)

About the Author

Chris Spear has been working in the ASIC design and verification field for 30 years. He started his career with Digital Equipment Corporation (DEC) as a / CAD Engineer on DECsim, connecting the first Zycad box ever sold, and then a hardware Verification engineer for the VAX 8600, and a hardware behavioral simulation accelerator. He then moved on to Cadence where he was an Application Engineer for Verilog-XL, followedby a stint at Viewlogic. Chris is currently employed at Synopsys Inc. as a Verification Consultant, a title he created a dozen years ago. He has authored the first and second editions of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features. Chris earned a BSEE from Cornell University in 1981. In his spare time, Chris enjoys road biking in the mountains and traveling with his wife.

Greg Tumbush has been designing and verifying ASICs and FPGAs for 13 years. After working as a researcher in the Air Force Research Labs (AFRL) he moved to beautiful Colorado to work with Astek Corp as a Lead ASIC Design Engineer. He then began a 6 year career with Starkey Labs, AMI Semiconductor, and ON Semiconductor where he was an early adopter of SystemC and SystemVerilog. In 2008, Greg left ON Semiconductor to form Tumbush Enterprises, LLCwhere he has been consulting clients in the areas of design, verification, and backend to ensure first pass success. He is also apart time Instructor at the University of Colorado, Colorado Springs where he teaches senior and graduate level digital design and verification courses. He has numerous publications which can be viewed at www.tumbush.com. Greg earned a Ph.D. from the University of Cincinnati in 1998.

Table of Contents

Verification Guidelines.- Data Types.- Procedural Statements and Routines.- Connecting the Testbench and Design.- Basic OOP.- Randomization.- Threads and Interprocess Communication.- Advanced OOP and Testbench Guidelines.- Functional Coverage.- Advanced Interfaces.- A Complete SystemVerilog Testbench.- Interfacing with C/C++.

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