Title: Writing Testbenches: Functional Verification of HDL Models / Edition 2, Author: Janick Bergeron
Title: Writing Testbenches using SystemVerilog / Edition 1, Author: Janick Bergeron
Title: Writing Testbenches using SystemVerilog / Edition 1, Author: Janick Bergeron
Title: The e Hardware Verification Language / Edition 1, Author: Sasan Iman
Title: The e Hardware Verification Language, Author: Sasan Iman
Title: System-on-Chip Methodologies & Design Languages / Edition 1, Author: Peter J. Ashenden
Title: System-on-Chip Methodologies & Design Languages / Edition 1, Author: Peter J. Ashenden
Title: System Specification & Design Languages: Best of FDL'02 / Edition 1, Author: Eugenio Villar
Title: System Specification & Design Languages: Best of FDL'02 / Edition 1, Author: Eugenio Villar
Title: System on Chip Design Languages: Extended papers: best of FDL'01 and HDLCon'01 / Edition 1, Author: Anne Mignotte
Title: System on Chip Design Languages: Extended papers: best of FDL'01 and HDLCon'01 / Edition 1, Author: Anne Mignotte
Title: Practical Formal Methods for Hardware Design, Author: Carlos Delgado Kloos
Title: Optimized ASIP Synthesis from Architecture Description Language Models / Edition 1, Author: Oliver Schliebusch
Title: Optimized ASIP Synthesis from Architecture Description Language Models / Edition 1, Author: Oliver Schliebusch
Title: Modeling with an Analog Hardware Description Language / Edition 1, Author: H. Alan Mantooth
Title: Higher-Level Hardware Synthesis / Edition 1, Author: Richard Sharp
Title: High-Level System Modeling: Specification Languages / Edition 1, Author: Jean-Michel Bergï
Title: High-Level Synthesis: from Algorithm to Digital Circuit / Edition 1, Author: Philippe Coussy
Title: High-Level Synthesis: from Algorithm to Digital Circuit / Edition 1, Author: Philippe Coussy
Title: Hardware Description Languages and their Applications: Specification, modelling, verification and synthesis of microelectronic systems / Edition 1, Author: Carlos Delgado Kloos

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