A Guide to VHDL

A Guide to VHDL is intended for the working engineer who needs to develop, document, simulate and synthesize a design using the VHDL language. It is for system and chip designers who are working with VHDL CAD tools, and who have some experience programming in Fortran, Pascal, or C and have used a logic simulator. A Guide to VHDL includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises invluded in the chapte...