High Speed CMOS Design Styles is written for the graduate-level student or practicing engineer who is primarily interested in circuit design. It is intended to provide practical reference, or 'horse-sense', to mechanisms typically described with a more academic slant. This book is organized so that it can be used as a textbook or as a reference book. High Speed CMOS Design Styles provides a survey of design styles in use in industry, specifically in the high speed microprocessor design community. Logic circuit structures, I/O and interface, clocking, and timing schemes are reviewed and described. Characteristics, sensitivities and idiosyncrasies of each are highlighted. High Speed CMOS Design Styles also pulls together and explains contributors to performance variability that are associated with process, applications conditions and design. Rules of thumb and practical references are offered. Each of the general circuit families is then analyzed for its sensitivity and response to this variability. High Speed CMOS Design Styles is an excellent source of ideas and a compilation of observations that highlight how different approaches trade off critical parameters in design and process space.
|Product dimensions:||6.10(w) x 9.25(h) x 0.03(d)|
Table of ContentsPreface. 1. Process Variability. 2. Non-Clocked Logic Styles. 3. Clocked Logic Styles. 4. Circuit Design Margin and Design Variability. 5. Latching Strategies. 6. Interface Techniques. 7. Clocking Styles. 8. Slack Borrowing and Time Stealing. 9. Future Technology. Index.