Power Efficiency in Broadband Wireless Communications

Power Efficiency in Broadband Wireless Communications


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Product Details

ISBN-13: 9781466595484
Publisher: Taylor & Francis
Publication date: 09/02/2014
Pages: 340
Product dimensions: 6.10(w) x 9.20(h) x 0.90(d)

About the Author

Pooria Varahram received his B.Sc. in electrical and electronics engineering from Khajenasir University of Technology in 2002, his M.Sc. in telecommunications engineering from Tarbiat Modares University in 2004, and Ph.D. in wireless communication engineering from the University of Putra Malaysia (UPM) in 2010. He has more than five years of experience in designing and developing a range of electronic and telecommunication-related projects. He has completed his Post PhD in UPM in 2012. He is now senior lecturer in UPM since January 2013. His research interests are PAPR reduction in OFDM systems, linearization of power amplifiers, and microwave power amplifier design.

Table of Contents

Evolution of Multiplexing Techniques in Wireless Communication Systems
Evolution of Mobile Cellular Networks
First-Generation Cellular Systems
Second-Generation Cellular Systems
Third-Generation Cellular Systems
Future Broadband Wireless Communication
Evolution of Multiplexing Techniques
Frequency Division Multiplexing Access (FDMA) Technique
Time Division Multiplexing Access (TDMA) Technique
Code Division Multiple Access (CDMA) Technique
Orthogonal Frequency Division Multiplexing (OFDM) in 4G
OFDM Pros and Cons
Key Technologies
Generalized Frequency Division Multiplexing (GFDM)
Multiple Input Multiple Output (MIMO)
Space Time and Space Frequency Transmission over MIMO Networks

Orthogonal Frequency Division Multiplexing Theory
History of OFDM
OFDM Blocks
OFDM Mathematical Analysis and Measurements

Power Amplifiers in Wireless Communications
High Power Amplifiers
Nonlinearity of Power Amplifiers
Characteristics of Power Amplifiers
Drain Efficiency
Power-Added Efficiency (PAE)
Output Power
Signal Gain
Trade-Off between Linearity and Efficiency
Power Amplifier Two-Tone Test
Classification of Power Amplifiers
Class A
Class B
Class AB
Class C
Class F
Other High-Efficiency Classes
Power Amplifier Memory Effects
Electrical Memory Effects
Electrothermal Memory Effects
Modeling Power Amplifiers
Modeling Power Amplifiers without Memory
Power Amplifier Model with Memory Effects
Power Amplifier Simulations

Peak-to-Average Power Ratio
The Effect of High PAPR on Power Amplifiers
PAPR Reduction Techniques
Distortion-Based PAPR Reduction Techniques
Clipping Method
Windowing Method
Companding Method
Distortionless-Based PAPR Reduction Methods
Coding Method
Active Constellation Extension
Partial Transmit Sequence
Enhanced PTS
Selected Mapping Method
Tone Reservation Method
Dummy Signal Insertion Method
A Discussion on the Current PAPR Reduction Solutions
Design of the Proposed DSI-SLM Scheme
The Proposed DSI-SLM Scheme
DSI-SLM Computational Complexity
Simulation Results and Analysis
Results Discussion
The Optimum Phase Sequence with the Dummy Sequence Insertion Scheme
Design of the OPS-DSI Scheme
System Performance of the OPS-DSI Scheme
OPS-DSI Side Information
Advantages and Disadvantages of the Proposed OPS-DSI Scheme
OPS-DSI Computational Complexity
Simulation Results and Analysis
Results Discussion

Peak-to-Average Power Ratio Implementation
Software Implementation Design
MATLAB Simulation Design
C++ Implementation Design
Implementation Platform
Hardware Complexity
Hardware Implementation
Field Programmable Gate Array
The System Generator Tool
System Generator Design Flow
The Prototype of the Dummy Signal Insertion with Selected Mapping Scheme
The Inverse Fast Fourier Transform Prototype
Using AccelDSP Software to Prototype IFFT
Prototype of the Conventional Selected Mapping Method
Implementation of the DSI-SLM Scheme
Hardware Resource Consumption
FPGA Implementation of the Optimum Phase Sequence with the Dummy Sequence Insertion Scheme
Implementation of the OPS-DSI Transmitter
Implementation of the OPS-DSI Receiver
Implementation of Complex Division in the Receiver
Newton-Raphson Division
Error Analysis
Initial Approximation Techniques
Hardware Structure of the Complex Divider
Divisor Scaling
Newton-Raphson Method
Postscaling of Division Values
Hardware Resource Consumption of the OPS-DSI Scheme

Power Amplifier Linearization
Power Amplifier Linearization Techniques
6.2.1 The Feedback Linearization Technique
6.2.2 Linear Amplification with Nonlinear
6.2.3 Feedforward Linearizers
6.2.4 Predistortion Linearizers
6.2.5 Digital Predistortion
6.2.6 Memory Polynomial Predistortion
6.2.7 Complex Gain Predistortion
6.2.8 The Digital Predistortion Linearization Method
6.2.9 Complex Gain Memory Predistortion
Simulation Results of Applying Complex Gain
Memory Predistortion

Digital Predistortion Implementation
Simulation with Xilinx Blocksets
7.2.1 System Generator
Xilinx Embedded Development Kit
Field Programmable Gate Array
7.4.1 Description
7.4.2 Functional Description
Complex Gain Memory Predistortion Implementation
7.5.1 Complex Multiplier
7.5.2 Lookup Table (LUT)
Complex Divider Implementation
Results of FPGA Implementation
Digital Signal Processing Implementation of Digital Predistortion
DP Block Design
7.9.1 Linear Convergence Adaptation Algorithm
7.9.2 Adaptation Block
7.9.3 Complex Multiplier
7.9.4 Saleh Model Amplifier
7.9.5 The IQSR Block

Experimental Results
Experimental Setup
Experimental Results
Comparison between Simulation and Experimental Results


Complex Baseband Representation of Bandpass Signals


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