Sigma Delta A/D Conversion for Signal Conditioning

1.1 Background Moore’s Law predicts a decrease by a factor of two in the feature size of CMOS te— nology every three years and has been valid for years. It implies a doubling of the — eration speed and a four times higher transistor count per unit of area, every three years. The combination leads to an eight times higher processing capability per unit of area. This on—going miniaturization allows the integration of complex electronic systems with millions of transistors (Very—Large—Scale—In...