Pub. Date:
Springer US
Wafer Level 3-D ICs Process Technology / Edition 1

Wafer Level 3-D ICs Process Technology / Edition 1

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Product Details

ISBN-13: 9780387765327
Publisher: Springer US
Publication date: 09/19/2008
Series: Integrated Circuits and Systems
Edition description: 2009
Pages: 410
Product dimensions: 6.40(w) x 9.30(h) x 0.90(d)
Age Range: 3 Months

Table of Contents

Overview of Wafer Level 3-D ICs.- Monolithic 3-D Integrated Circuits.- Stacked CMOS Technologies.- Wafer Bonding Technologies and Strategies for 3-D ICs.- Through Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies.- Cu Wafer Bonding for 3-D ICs Applications.- Cu/Sn Solid-Liquid Interdiffusion Bonding.- An SOI-Based 3-D Circuit Integration Technology.- 3-D Fabrication Options for High Performance CMOS Technology.- 3-D Integration Based upon Dielectric Adhesive Bonding.- Direct Hybrid Bonding.- 3-D Memory.- Circuit Architectures for 3-D Integration.- Thermal Challenges of 3-D ICs.- Status and Outlook.

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