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9781558608658
The Student's Guide to VHDL / Edition 2 available in Paperback
- ISBN-10:
- 1558608656
- ISBN-13:
- 9781558608658
- Pub. Date:
- 05/19/2008
- Publisher:
- Elsevier Science
- ISBN-10:
- 1558608656
- ISBN-13:
- 9781558608658
- Pub. Date:
- 05/19/2008
- Publisher:
- Elsevier Science
The Student's Guide to VHDL / Edition 2
by Peter J. Ashenden
Peter J. Ashenden
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Overview
The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for computer organization and digital design courses.Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised. In The Student's Guide to VHDL, 2nd Edition, we have included a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study helps to better serve the educational market. Currently, most college courses do not formally address the details of design flow. Students may be given informal guidance on how to proceed with lab projects. In many cases, it is left to students to work it out for themselves. The case study in The Student's Guide provides a reference design flow that can be adapted to a variety of lab projects.
Product Details
| ISBN-13: | 9781558608658 |
|---|---|
| Publisher: | Elsevier Science |
| Publication date: | 05/19/2008 |
| Series: | Systems on Silicon |
| Edition description: | REV |
| Pages: | 528 |
| Product dimensions: | 7.30(w) x 9.10(h) x 1.30(d) |
About the Author
Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.
Read an Excerpt
From Chapter 7: Packages and Use Clauses
...Subprograms in Package Declarations
Another kind of declaration that may be included in a package declaration is a subprogram declaration—either a procedure or a function declaration. This ability allows us to write subprograms that implement useful operations and to call them from a number of different modules. An important use of this feature is to declare subprograms that operate on values of a type declared by the package. This gives us a way of conceptually extending VHDL with new types and operations, so-called abstract data types.
An important aspect of declaring a subprogram in a package declaration is that we only write the header of the subprogram, that is, the part that includes the name and the interface list defining the parameters (and result type for functions). We leave out the body of the subprogram. The reason for this is that the package declaration, as we mentioned earlier, provides only the external view of the items it declares, leaving the implementation of the items to the package body. For items such as types and signals, the complete definition is needed in the external view. However, for subprogram. As users of a subprogram, we need not be concerned with how it achieves its effect or calculates its result. This is an example of a general principle called information hiding: making an interface visible but hiding the details of implementation. To illustrate this idea, suppose we have a package declaration that defines a bit-vector subtype:
subtype word32 is bit_vector(31 downto 0);
We can include in the package a procedure to do addition onWord32 values that represent signed integers. The procedure declaration in the package declaration is:
procedure add ( a, b : in word32; result : out word32; overflow : out boolean );
Note that we do not include the keyword is or any of the local declarations or statements needed to perform the addition. These are deferred to the package body. All we include is the description of the formal parameters of the procedure. Similarly, we might include a function to perform an arithmetic comparison of two word32 values:
function "<" ( a, b : in word 32 ) return boolean;
Again, we omit the local declarations and statements, simply specifying the formal parameters and the result type of the function.
Constants in Package Declarations
Just as we can apply the principle of information hiding to subprograms declared in a package, we can also apply it to constants declared in a package. The external view of a constant is just its name and type. We need to know these in order to use it, but we do not actually need to know its value. This may seem strange at first, but if we recall that the idea of introducing constant declarations in the first place was to avoid scattering literal values throughout a model, it makes more sense. We defer specifying the value of a constant declared in a package by omitting the initialization expression, for example:
constant max_buffer_size : positive;
This defines the constant to be a positive integer value. However, since we cannot see the actual value, we are not tempted to write the value as an integer literal in a model that uses the package. The specification of the actual value is deferred to the package body; where it is not visible to a model that uses the package. Given the above deferred constant in a package declaration, the corresponding package body must include the full constant declaration, for example:
constant max_buffer_size : positive := 4096;
Note that we do not have to defer the value in a constant declaration—it is optional...
Table of Contents
Preface xiii
Fundamental Concepts 1
Modeling Digital Systems 1
Domains and Levels of Modeling 3
Modeling Example 3
Modeling Languages 7
VHDL Modeling Concepts 7
Elements of Behavior 8
Elements of Structure 10
Mixed Structural and Behavioral Models 12
Test Benches 13
Analysis, Elaboration and Execution 14
Learning a New Language: Lexical Elements and Syntax 16
Lexical Elements 17
Comments 17
Identifiers 19
Reserved Words 20
Special Symbols 22
Numbers 22
Characters 23
Strings 23
Bit Strings 24
Syntax Descriptions 26
Exercises 29
Scalar Data Types and Operations 31
Constants and Variables 31
Constant and Variable Declarations 31
Variable Assignment 33
Scalar Types 34
Type Declarations 34
Integer Types 35
Floating-Point Types 38
Physical Types 39
Time 42
Enumeration Types 43
Characters 44
Booleans 46
Bits 47
Standard Logic 48
Condition Conversion 49
Type Classification 50
Subtypes 51
Type Qualification 53
Type Conversion 53
Attributes of Scalar Types 54
Expressions and Predefined Operations 57
Exercises 61
Sequential Statements 65
If Statements 65
Case Statements 68
Null Statements 74
Loop Statements 75
Exit Statements 76
Next Statements 79
While Loops 80
For Loops 82
Summary of Loop Statements 85
Assertion and Report Statements 85
Exercises 92
Composite Data Types and Operations 95
Arrays 95
Multidimensional Arrays 98
Array Aggregates 99
Array Attributes 103
Unconstrained Array Types 105
Predefined Array Types 106
Strings 106
Boolean Vectors, Integer Vectors, Real Vectors, and Time Vectors 106
Bit Vectors 107
Standard-Logic Arrays 107
String and Bit-String Literals 108
Unconstrained Array Element Types 109
Unconstrained Array Ports 111
Array Operations and Referencing 114
Logical Operators 114
Shift Operators 116
Relational Operators 117
Maximum and Minimum Operations 118
The Concatenation Operator 119
To_String Operations 119
Array Slices 120
Array Type Conversions 121
Arrays in Case Statements 124
Matching Case Statements 125
Records 127
Record Aggregates 130
Unconstrained Record Element Types 130
Exercises 133
Basic Modeling Constructs 135
Entity Declarations and Architecture Bodies 135
Concurrent Statements 139
Signal Declarations 139
Behavioral Descriptions 141
Signal Assignment 141
Conditional Signal Assignments 144
Selected Signal Assignments 145
Signal Attributes 147
Wait Statements 149
Delta Delays 153
Transport and Inertial Delay Mechanisms 156
Process Statements 162
Concurrent Signal Assignment Statements 164
Concurrent Simple Signal Assignments 164
Concurrent Conditional Signal Assignment 165
Concurrent Selected Signal Assignments 169
Concurrent Assertion Statements 171
Entities and Passive Processes 172
Structural Descriptions 174
Design Processing 184
Analysis 184
Design Libraries and Contexts 186
Elaboration 188
Execution 191
Exercises 192
Subprograms 201
Procedures 201
Return Statement in a Procedure 206
Procedure Parameters 207
Signal Parameters 211
Default Values 214
Unconstrained Array Parameters 215
Summary of Procedure Parameters 218
Concurrent Procedure Call Statements 219
Functions 221
Functional Modeling 224
Pure and Impure Functions 224
The Function now 226
Overloading 227
Overloading Operator Symbols 228
Visibility of Declarations 230
Exercises 234
Packages and Use Clauses 239
Package Declarations 239
Subprograms in Package Declarations 244
Constants in Package Declarations 244
Package Bodies 246
Local Packages 249
Use Clauses 251
Visibility of Used Declarations 255
Exercises 258
Resolved Signals 261
Basic Resolved Signals 261
Composite Resolved Subtypes 266
Summary of Resolved Subtypes 271
IEEE std_logic_1164 Resolved Subtypes 272
Resolved Signals, Ports, and Parameters 274
Resolved Ports 276
Driving Value Attribute 279
Resolved Signal Parameters 280
Exercises 281
Predefined and Standard Packages 287
The Predefined Packages standard and env 287
IEEE Standard Packages 290
Standard VHDL Mathematical Packages 290
Real Number Mathematical Package 290
Complex Number Mathematical Package 293
The std_logic_1164 Multivalue Logic System 295
Standard Integer Numeric Packages 298
Package Summary 307
Operator Overloading Summary 307
Conversion Function Summary 309
Strength Reduction Function Summary 311
Exercises 312
Aliases 315
Aliases for Data Objects 315
Aliases for Non-Data Items 320
Exercises 323
Generic Constants 325
Generic Constants 325
Exercises 332
Components and Configurations 335
Components 335
Component Declarations 335
Component Instantiation 337
Packaging Components 338
Configuring Component Instances 340
Basic Configuration Declarations 340
Configuring Multiple Levels of Hierarchy 343
Direct Instantiation of Configured Entities 346
Generic and Port Maps in Configurations 347
Deferred Component Binding 353
Exercises 355
Generate Statements 359
Generating Iterative Structures 359
Conditionally Generating Structures 365
Exercises 372
Design for Synthesis 375
Synthesizable Subsets 375
Use of Data Types 376
Scalar Types 377
Composite and Other Types 378
Interpretation of Standard Logic Values 379
Modeling Combinational Logic 380
Modeling Sequential Logic 383
Modeling Edge-Triggered Logic 384
Level-Sensitive Logic and Inferring Storage 392
Modeling State Machines 394
Modeling Memories 396
Synthesis Attributes 400
Metacomments 410
Exercises 411
Case Study: System Design Using the Gumnut Core 413
Overview of the Gumnut 413
Instruction Set Architecture 413
External Interface 418
The Gumnut Entity Declaration 420
Instruction and Data Memories 421
A Digital Alarm Clock 425
System Design 425
Synthesizing and Implementing the Alarm Clock 433
Exercises 435
Standard Packages 437
The Predefined Package standard 437
The Predefined Package env 441
The Predefined Package textio 441
Standard VHDL Mathematical Packages 443
The math_real Package 443
The math_complex Package 445
The std_logic_1164 Multivalue Logic System Package 446
Standard Integer Numeric Packages 450
The numeric_bit Package 450
The numeric_std Package 456
The numeric_bit_unsigned Package 457
The numeric_std_unsigned Package 459
VHDL Syntax 461
Design File 463
Library Unit Declarations 463
Declarations and Specifications 465
Type Definitions 468
Concurrent Statements 470
Sequential Statements 472
Interfaces and Associations 475
Expressions and Names 476
Answers to Exercises 479
References 497
Index 499
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