CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test / Edition 1

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test / Edition 1

ISBN-10:
904817855X
ISBN-13:
9789048178551
Pub. Date:
12/01/2010
Publisher:
Springer Netherlands
ISBN-10:
904817855X
ISBN-13:
9789048178551
Pub. Date:
12/01/2010
Publisher:
Springer Netherlands
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test / Edition 1

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test / Edition 1

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Overview

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.


Product Details

ISBN-13: 9789048178551
Publisher: Springer Netherlands
Publication date: 12/01/2010
Series: Frontiers in Electronic Testing , #40
Edition description: Softcover reprint of hardcover 1st ed. 2008
Pages: 194
Product dimensions: 6.10(w) x 9.20(h) x 0.60(d)

About the Author

Prof. Sachdev has authored several successful books with Springer

Table of Contents

and Motivation.- SRAM Circuit Design and Operation.- SRAM Cell Stability: Definition, Modeling and Testing.- Traditional SRAM Fault Models and Test Practices.- Techniques for Detection of SRAM Cells with Stability Faults.- Soft Errors in SRAMs: Sources, Mechanisms and Mitigation Techniques.
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