Concurrency and Hardware Design: Advances in Petri Nets

As CMOS semiconductor technology strides towards billions of transistors on a single die new problems arise on the way. They are concerned with the — minishing fabrication process features, which affect for example the gate—to—wire delay ratio. They manifest themselves in greater variations of size and operating parameters of devices, which put the overall reliability of systems at risk. And, most of all, they have tremendous impact on design productivity, where the costs of utilizing the g...