Debugging becomes more and more the bottleneck to chip design productivity, especially while developing modern complex integrated circuits and systems at the Electronic System Level (ESL). Today, debugging is still an unsystematic and lengthy process. Here, a simple reporting of a failure is not enough, anymore. Rather, it becomes more and more important not only to find many errors early during development but also to provide efficient methods for their isolation. In Debugging at the Electronic System Level the state-of-the-art of modeling and verification of ESL designs is reviewed. There, a particular focus is taken onto SystemC. Then, a reasoning hierarchy is introduced. The hierarchy combines well-known debugging techniques with whole new techniques to improve the verification efficiency at ESL. The proposed systematic debugging approach is supported amongst others by static code analysis, debug patterns, dynamic program slicing, design visualization, property generation, and automatic failure isolation. All techniques were empirically evaluated using real-world industrial designs. Summarized, the introduced approach enables a systematic search for errors in ESL designs. Here, the debugging techniques improve and accelerate error detection, observation, and isolation as well as design understanding.
|Product dimensions:||6.10(w) x 9.25(h) x (d)|
Table of ContentsList of Figures. List of Tables. Preface. Acknowledgements.
1. INTRODUCTION; 1 General Objective of the Book; 2 Summary of Contributions; 3 Book Outline. 2. ESL DESIGN AND VERIFICATION; 1 ESL Design; 2 ESL Verification; 3 Our Debugging Approach. 3. EARLY ERROR DETECTION; 1 Deduction Techniques in a Nutshell; 2 Static Analysis Framework; 3 SystemC Design Analysis System; 4 Experimental Results; 5 Summary and Future Work. 4. HIGH-LEVEL DEBUGGING AND EXPLORATION; 1 Observation Techniques in a Nutshell; 2 System-Level Debugging; 3 High-Level SystemC Debugging; 4 Experimental Results; 5 Summary and Future Work. 5. LEARNING ABOUT THE DESIGN; 1 Induction Techniques in a Nutshell; 2 Automatic Generation of Properties; 3 Dynamic Invariant Analysis on Simulation Traces; 4 Experimental Results; 5 Summary and Future Work. 6. ISOLATING FAILURE CAUSES; 1 Experimentation Techniques in a Nutshell; 2 Automatic Isolation of Failure Causes; 3 Automatic Isolation of Failure Causes in SystemC; 4 Experimental Results; 5 Summary and Future Work. 7. SUMMARY AND CONCLUSION.
Appendix A. FDC Language ; 1 FDC Syntax ; 2 FDC Semantic.
Appendix B. Debug Pattern Catalog; 1 General Format; 2 COMPETITION Pattern; 3 TIMELOCK Pattern.
References. List of Acronyms. Index of Symbols. Index.